rockbox/firmware/target/arm/imx31/debug-imx31.c, branch master

i.MX31: Restore screen clearing in DVFS/DPTC debug screen

2017-01-30T00:53:49+00:00

Somewhere along the line the screen stopped being cleared prior to
writing new text on each frame, which left visible bits of
previously-displayed text when it changed.

Change-Id: I344e03c234daa77f4e64ed89281c40db887e4498

Fix more reds.

2014-03-03T19:26:08+00:00

Change-Id: I4b58dda0953b7f9799238c32b78037b0a5403c04

remove debug-target.h

2012-05-07T04:55:59+00:00

imx31: move DEBUG_CANCEL definition to .c

2012-01-04T06:33:59+00:00

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@31564 a1c6a512-1295-4272-9138-f99709370657

Move dbg_hw_info() into target tree. FS#11735 by me

2011-06-05T10:26:06+00:00

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@29964 a1c6a512-1295-4272-9138-f99709370657

i.MX31: Add a debug menu to play around with DVFS/DPTC settings for fun, testing or benchmarking purposes. Can set the CPU frequency working point, whether DPTC voltage scaling is enabled and change the software-programmable load tracking weights.

2011-01-22T16:58:17+00:00

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@29113 a1c6a512-1295-4272-9138-f99709370657

move dbg_ports() from apps/menu_debug.c to target tree. FS#11712 by me.

2010-11-06T14:24:25+00:00

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28522 a1c6a512-1295-4272-9138-f99709370657

Move c/h files implementing/defining standard library stuff into a new libc directory, also standard'ify some parts of the code base (almost entirely #include fixes).

2010-05-06T21:04:40+00:00

This is to a) to cleanup firmware/common and firmware/include a bit, but also b) for Rockbox as an application which should use the host system's c library and headers, separating makes it easy to exclude our files from the build.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25850 a1c6a512-1295-4272-9138-f99709370657

i.MX31/Gigabeat S: This should fix stability problems. One problem was to start using the DVFS controller properly so that interrupts will be masked at the lowest and highest frequency indexes. Millions of useless interrupts were occurring at 132MHz because its index was 2, not 3, which masks it automatically when it can't go slower. Stopping the flood was enough to actually see the difference in general. IRQ must be disabled when fiddling with the CCM registers and only enabled when waiting for voltage ramp as having them enables also causes spurious DVFS ints. Implement interruptible ISR pro/epilogue more safely (always using IRQ stack even in SVC mode handling). Fix an improper inequality in DVFS code (which set regs for down when going up and v.v.). Misc. support changes. Have internal tables take less RAM.

2010-05-06T03:23:51+00:00

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25837 a1c6a512-1295-4272-9138-f99709370657

i.MX31/Gigabeat S: Actually enable DPTC which can set optimal voltage for 528MHz. Requires an SPI and PMIC interface rework because of the low-latency needs for the DPTC to work best with minimal panicing. SPI can work with multitasking and asynchronously from interrupt handlers or normal code.

2010-05-04T10:07:53+00:00

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25800 a1c6a512-1295-4272-9138-f99709370657