rockbox/firmware/target/sh/system-target.h, branch master

Create fimrware/asm directory for assembly optimized stuff.

2012-01-22T17:46:44+00:00

This dir is suitable for stuff that doesn't fit the target tree, e.g. because
it also builds on hosted or otherwise. It also has a generic subfolder for
fallback C implementations so that not all archs need to provide asm files.

SOURCES should only contain "foo.c" where foo.c includes the specific
/foo.c files from the subdirs using the preprocessor. This way automatic
selection of asm versions or generic C verion is possible.

For the start, the thread support files are moved, since ASM threads can
be used on hosted platforms as well. Since core_sleep() remains platform
specific it's moved to the corresponding system.h headers.

Change-Id: Iebff272f3407a6eaafeb7656ceb0ae9eca3f7cb9

Commit to certain names for cache coherency APIs and discard the aliases.

2011-12-17T07:27:24+00:00

Wouldn't surprise me a bit to get some non-green.


git-svn-id: svn://svn.rockbox.org/rockbox/trunk@31339 a1c6a512-1295-4272-9138-f99709370657

Byteswap routines don't really need 'asm volatile', just 'asm' since it should be safe to move them for optimizing. Clean up the line endings for ARM.

2011-02-25T00:46:39+00:00

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@29394 a1c6a512-1295-4272-9138-f99709370657

Use __builtin_constant_p() to select the best byteswapping method: constant or target optimized. Same macro can then be used for constant values and inits as well as non-constant.

2011-01-30T00:58:45+00:00

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@29171 a1c6a512-1295-4272-9138-f99709370657

Replace 1UL in BIT_N with 1U to avoid turning it into a 64-bit operation on 64-bit sim targets.

2009-06-06T00:58:57+00:00

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21197 a1c6a512-1295-4272-9138-f99709370657

Add a system-wide BIT_N macro, implemented via an LUT on SH, and use it in the TAGCACHE_IS_* macros in place of per-set LUTs, removing duplication of data between those LUTs and the mask values used on other targets.

2009-06-06T00:00:58+00:00

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21195 a1c6a512-1295-4272-9138-f99709370657

Make basic cache functions into calls, and get rid of CACHE_FUNCTION_WRAPPERS and CACHE_FUNCTIONS_AS_CALL macros. Rename flush/invalidate_icache to cpucache_flush/invalidate. They're inlined only if an implementation isn't provided by defining HAVE_CPUCACHE_FLUSH/INVALIDATE.

2009-02-11T12:55:51+00:00

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19971 a1c6a512-1295-4272-9138-f99709370657

Updated our source code header to explicitly mention that we are GPL v2 or

2008-06-28T18:10:04+00:00

later. We still need to hunt down snippets used that are not. 1324 modified
files...
http://www.rockbox.org/mail/archive/rockbox-dev-archive-2008-06/0060.shtml


git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17847 a1c6a512-1295-4272-9138-f99709370657

Do core interrupt masking in a less general fashion and save some instructions to decrease size and speed things up a little bit. Small fix to a few places where interrupts would get enabled again where they shouldn't have been (context switching calls when disabled).

2008-03-26T01:50:41+00:00

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16811 a1c6a512-1295-4272-9138-f99709370657

A bit of clarification of code origin. No code change.

2007-04-15T22:52:42+00:00

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13173 a1c6a512-1295-4272-9138-f99709370657