rockbox/utils/hwstub/stub, branch wolf3d

MIPS: fix memset()

2018-09-07T07:43:05+00:00

swr/swl instructions used for word aligning were wrong. This
made memset() terribly broken. I can't imagine how it went
uncaught for soooo long. Spotted by Solomon Peachy.

I run unit tests for alignments 0,1,2,3
size 1, 2, 3, 4, 5, 63, 64, 65, 127, 128, 129;
and fill pattern 0x00 and other (since 0 is special case in this
implementation).

Change-Id: I513a10734335fe97734c10ab5a6c3e3fb3f4687a

ATJ hwstub: Add cache coherency

2017-09-15T19:44:59+00:00

All the hard work was done by pamaury. I simply added proper
defines.

Change-Id: Ib374eea7cd20f35518ad8a68d771c57c54ae01ca

hwstub: rewrite exception catching

2017-01-24T14:34:19+00:00

Since we can catch exceptions like data aborts on read/write, it takes very
little to also catch exceptions in calls. When extending this with the catching
of illegal instructions, the call instruction now becomes much more robust and
also for address and instruction probing. Since we can catch several types of
exception, rename set_data_abort_jmp to set_exception_jmp. At the same time,
simplify the logic in read/write request handlers. Also fix a bug in ARM
jump code: it was using
  stmia r1, {..., pc}
as if pc would get current pc + 8 but this is actually implementation defined
on older ARMs (typically pc + 12) and deprecated on newer ARMs, so rewrite the
code avoid that. The set_exception_jmp() function now also reports the exception
type.

Change-Id: Icd0dd52d2456b361b27c4776be09c3d13528ed93

hwstub/jz460b: implement exception recovery

2017-01-24T14:34:19+00:00

Now that we now that jz4760b implements EBASE, we can use it to rebase
exceptions to use a k1seg address, that maps to the physical address of the
TCSM0. It requires to enable HAB1 to have this translation. This most the most
inefficient way to access tighly coupled memory ever, but it works.

Change-Id: I894ca929c9835696102eb2fef44b06e6eaf96d44

hwstub/jz4760b: build packtools automatically if neeeded

2017-01-24T14:31:05+00:00

Change-Id: I543e405bf75868d0f7509a35e08fe31ed253e0e6

hwstub: add verbose mode to make

2017-01-24T14:31:05+00:00

Use make V=1 to print all commands

Change-Id: I28bd4151178413f10ddab292f1d582a9d019f5ea

hwstub: add support for coprocessor operations

2017-01-24T14:25:14+00:00

At the moment the stub only implement them for MIPS.

Change-Id: Ica835a0e9c70fa5675c3d655eae986e812a47de8

hwstub: add the possibility to flush caches before exec

2017-01-24T14:25:14+00:00

This is needed on the jz4760b because if some data is loaded to DRAM, then it
is cached and a disaster lurks if dcaches/icache are not flushed. Targets that
needs this must define CONFIG_FLUSH_CACHES in target-config.h and implement
target_flush_caches(). Currently MIPS has some generic code for mips32r1 that
requires to define {D,I}CACHE_SIZE and {D,I}CACHE_LINE_SIZE in target-config.h

Change-Id: I5a3fc085de9445d8c8a2eb61ae4e2dc9bb6b4e8e

hwstub: add jz4760b stub

2017-01-24T14:22:27+00:00

The stub is quite versatile: it can be loaded using bootrom or another other
means (like factory boot on Fiio X1). It relocates itself to TCSM0 and provides
basic functionality (it does not recover from failed read/writes at the moment).

Change-Id: Ib646a4b43fba9358d6f93f0f73a5c2e9bcd775a7

ATJ hwstub make irq based usb driver work

2016-11-10T12:57:02+00:00

0e2b490 introduced rework of usb driver which was broken. It was reverted
in f2da975 to restore hwstub functionality on ATJ.

This commit reenables usb rework AND fixes remining issues.
The problem was with 0 length OUT thransfers. Additionally
a few cleanups were made.

Change-Id: I529ea9ad6540509e9287ca7e1cd2b44369b03cbb