Change-Id: I083024662f3c085f7bcd2f85b0a68de85725b0f3

Add lua code to check whether ei/di and ext instructions are supported. This
is unclear since xburst is somewhere between mips32r1 and mips32r2. Details
results are below, but in summary: they don't work (ei has no effect, di/ext
cause illegal instruction exceptions)

> ./hwstub_shell -q -b -e 'require("jz/misc"); JZ.misc.enable_sram()' \
  -f lua/xburst.lua -e "XBURST.test_ext_inst(0xb32d0000)"
[...]
Selecting soc jz4760b. Redirecting HW to hwstub.soc.jz4760b
  data: d7168acf
error: lua/xburst.lua:209: call failed
trapped exception in call

> ./hwstub_shell -q -b -e 'require("jz/misc"); JZ.misc.enable_sram()' \
  -f lua/xburst.lua -e "XBURST.test_ei_di_inst(0xb32d0000)"
[...]
Selecting soc jz4760b. Redirecting HW to hwstub.soc.jz4760b
Testing ei
  Test SR
    Enable interrupts with CP0
    SR: 0x1
    Disable interrupts with CP0
    SR: 0x0
  Test ei/di
    Enable interrupts with ei
    SR: 0x0
    Disable interrupts with di
error: lua/xburst.lua:244: call failed
trapped exception in call

Change-Id: I2e162b5dd5e70488bcd8b58f3ca401a3ecab3c4b

Change-Id: I76f7cffc700e8051d02936c24e8a70a0f8925edf

Change-Id: I14987d9783dd371f4990a5bcfbfb2d1c0c9be213

The JZ misc allows to enable and test SRAM.
The XBurst code uses the coprocessor interface to analyse the cpu. It also
provides a test platform for various features like EBASE and exceptions.
I was able to test and confirm that on jz4760b (thus xburst), EBASE works
(but top 2 bits are not controllable and always 01). The processor claims
to support vector interrupts but this is untested. The values in ConfigX
are not to be trusted blindly, clearly some are wrong. I tried to use the
JZ4780 Config7 "ebase gate" to change bit 30 of EBASE but it does not work,
which suggests that JZ480 uses a newer version of XBurst. Detailled log below:

> ./hwstub_shell -q -f lua/xburst.lua -e "XBURST.init()"
[...]
XBurst:
  PRId: 0x2ed0024f
    CPU: JZ4760(B)
  Config: 0x80000483
    Architecture Type: MIPS32
    Architecture Level: Release 2 (or more)
    MMU Type: Standard TLB
  Config1: 0x3e63318a
    MMU Size: 32
    ICache
      Sets per way: 128
      Ways: 4
      Line size: 32
    DCache
      Sets per way: 128
      Ways: 4
      Line size: 32
    FPU: no
  Config2: 0x80000000
  Config3: 0x20
    Vectored interrupt: yes
  Config7: 0x0

> ./hwstub_shell -q -e 'require("jz/misc"); JZ.misc.enable_sram()' \
  -f lua/xburst.lua -e "XBURST.test_ebase(0x80000000);XBURST.test_ebase(0xb32d0000)
[...]
Testing EBASE...
  Disable BEV
  SR value: 0x2000fc00
  EBASE value: 0x80000000
    Value after writing 0x80000000: 0x80000000
    Value after writing 0x80040000: 0x80040000
  Test result: EBase seems to work
    Disable config7 gate: write 0x0 to Config7
    Value after writing 0xfffff000: 0xbffff000
    Enable config7 gate: write 0x80 to Config7
    Value after writing 0xc0000000: 0x80000000
  Config7 result: Config7 gate does not work
Exception test with EBASE at 0x80000000...
  Writing instructions to memory
  Old SR: 0x2000fc00
  New SR: 0xfc00
  EBASE: 80000000
  Before: cafebabe
  After: deadbeef
  Exception result: Exception and EBASE are working
Testing EBASE...
  Disable BEV
  SR value: 0x2000fc00
  EBASE value: 0x80000000
    Value after writing 0x80000000: 0x80000000
    Value after writing 0x80040000: 0x80040000
  Test result: EBase seems to work
    Disable config7 gate: write 0x0 to Config7
    Value after writing 0xfffff000: 0xbffff000
    Enable config7 gate: write 0x80 to Config7
    Value after writing 0xc0000000: 0x80000000
  Config7 result: Config7 gate does not work
Exception test with EBASE at 0xb32d0000...
  Writing instructions to memory
  Old SR: 0x2000fc00
  New SR: 0xfc00
  EBASE: b32d0000
  Before: cafebabe
  After: deadbeef
  Exception result: Exception and EBASE are working

Change-Id: I894227981a141a8c14419b36ed9f519baf145ad1

Change-Id: Ie46ec293fcd5a16143818e77cd6c79cc08620fb5

The jz code can do several useful things like dumping the IPL and SPL.
The Fiio code can play with backlight and has code do dump the IPL
and SPL with the correct parameters (extracted by reverse engineering).

Change-Id: I317b3174f5db8d38c9a56670c1d45565142ec208

Also use this opportunity to cleanup support for multiple devices: the shell
now supports dynamic changes in the device and will call init() everytime
a new device is selected, to prepare a new environment. The shell now
honors register width on register read/write. The shell also provides access
to variants as follows by creating a subtable under the register using the
variant type in UPPER case and having the same layout as a register.
For example if register HW.GPIO.DIR has variants "set" and "clr", those can
be used like this:
HW.GPIO.DIR.SET.write(0xff)
HW.GPIO.DIR.CLR.write(0xff00)

Change-Id: I943947fa98bce875de0cba4338e8b7196a4c1165

Change-Id: I5fbd1799b958bedbe74f91bdcdd8a544e15d2a78

With this you can upload and run code on DSP core in atj213x.

The files can be produced using as2181. You can download
this assembler from https://github.com/wodz/as2181
You should use extended mode (-x switch) since DSP core
in atj is non standard and uses 24bit operands.
PX register has different meaning as well and is used as MSB
when loading other registers with immediates (immediate field
is 16bit in instruction so to set register to 24bit value
you need to store MSB in PX prior to this).

MAC MR is 56bit accordingly.

HIP interface seems to be mapped at standard addresses
(except that regular 218x doesn't have HIP).

Have a fun!

Change-Id: I9a80ca0dd3718ba8435ae8579bfffa66e067e022