| Commit message (Collapse) | Author | Age |
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Change-Id: Ifc678166ac70cc8fc76897c76ccbc4bc3f88cc14
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If interrupts trigger during cache invalidation this could cause memory
corruption. This should be right fix for commit_discard_idcache in
contrast to 72ebcbf and c1ec1ec.
Change-Id: I141fb585004d4a1967b0a03bc37db3964d886564
Reviewed-on: http://gerrit.rockbox.org/345
Tested-by: Andrew Ryabinin <ryabinin.a.a@gmail.com>
Reviewed-by: Marcin Bukat <marcin.bukat@gmail.com>
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It seems something wrong with cache handling in rk27xx. OF always disable cache
before invalidating cache ways, therefore, now we do the same.
Hopefully this will fix cache handling, but I couldn't contend that it's really so.
Change-Id: I967c18211f0ddff689b6a17579fbe8685277f132
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This was commited by accident, sorry.
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This is work from FS#12431 synced to current HEAD and slightly
tweaked (gcc 4.6.2 -> 4.6.3, binutils 2.21.1 -> 2.22)
Change-Id: I76af91e80ac2a9c16a776c7f0a33cc51603bbf9b
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Change-Id: I6721227938955915fede32b6748802f7abf4b391
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The running count is only 16-bit wide, since the always tick
setting derives from the crystal clock at 24MHz the user timer
cannot be set lower than ~300Hz which is already too high.
Switch to the 32KHz crystal source to fix this.
Change-Id: Ie7775460b17ea7ab331738734e3d688ad5563857
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Several HM-801 DAPs have another buttons circuit.
This patch adds support for such devices so they could work properly.
Change-Id: Ic49e8e46b3e785b91c7c4706003fac3dbc20ae59
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Change-Id: Id084a7508093e1c7e94006a3adc3beba4025b8a6
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Change-Id: I327ddd5506598c80263424d85afa84cd3c9acfeb
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Change-Id: I9c0e1ecd04d1935825606e906e6a434a3afb2175
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Uses register polling method to decide when it's time to decode
RDS packets.
Change-Id: I1d3cc995ea3350ec7b101438b8f2027130d4a4c9
Reviewed-on: http://gerrit.rockbox.org/320
Reviewed-by: Lorenzo Miori <memorys60@gmail.com>
Tested-by: Lorenzo Miori <memorys60@gmail.com>
Reviewed-by: Thomas Martitz <kugel@rockbox.org>
Tested-by: Thomas Martitz <kugel@rockbox.org>
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Make set_sleep_timer a static function and only call
set_sleeptimer_duration externally, which is always called with minutes
values.
Change-Id: I985308bf014e354f91c47a0b2bf62f4f5a591919
Reviewed-on: http://gerrit.rockbox.org/327
Reviewed-by: Jonathan Gordon <rockbox@jdgordon.info>
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Previously TIMEOUT_BLOCK would be handled the same as TIMEOUT_NOBLOCK, i.e.
poll only without thread switch, which is rather unexpected from *_w_tmo()
functions. No current code doesn't call it that way yet.
Change-Id: I370ce0f752681122d197eadeee9ab17112647c20
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Change-Id: Ia435616872d5d4adb117d507bdb135bccf083b05
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We should cast to (volatile uint32_t*) here, because attempt to refer to volatile
object through use of an lvalue with non-volatile-qualified type will result in
undefined behavior.
Change-Id: I1b2e9688af11d3dcba518a5e31865d703b54b635
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Change-Id: Ia806994fc77c93fbd4c4c5ec234bb0f34641303a
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Use DMA engine for fullscreen updates and bypass mode for partial
updates. This gives major boost on rk27generic:
default ARM:AHB:APB 200:100:50
HEAD 1/1: 26.3fps 1/4: 105.0fps
patched 1/1: 116.5fps 1/4: 249.5fps
with freq scalling NORMAL mode ARM:AHB:APB 50:50:50
HEAD 1/1: 13.1fps 1/4: 52.5fps
patched 1/1: 54.5fps 1/4: 119.0fps
Tested on rk27generic noname DAP and on Hifimans.
Change-Id: Id9dd4d2d61542c7ea6b5c6336b170d6357cefde9
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This version resembles how OF handle cache invalidates.
This seems to fix mysterious data aborts on plugin/codec loading
after introducing frequency scaling.
Credit goes to mortalis for pinpointing the reason of aborts.
Change-Id: I3477b3f65d593d7b43c36a0b06d863f71f000812
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Change-Id: I3d700762a7f46e82ac99fed03e1aa9448b6cba47
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The functions document my reverse engineer findings about nand
controller. This code is commented out and is purely for reference
as FTL scheme is still unknown.
Change-Id: I70edeb4bfb0cbd51b6adc15afa7193dd8f71e8da
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Frequency scaling seems to be unstable and causes the device to
freeze. It is unclear why at the moment, perhaps we need to ramp
up the vddd voltage to avoid a false brownout ?
Change-Id: I7aaea9d7c213922a65250fe50775fb785d430226
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Change-Id: Ia6a869ec22734f95af2b453e01471b0656b7a273
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The divisor must be set only when auto-slow is disabled.
Change-Id: I31ed94f43a7c9deb80275dc73f8e3c78463b54c0
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Change-Id: I3a20b30e5707e98ffd5dfe3d0f267c5b2d4e7753
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Change-Id: I68258828afd3021bab2067e5af0a5dcd2d44de04
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Change-Id: I9eaa21ecfafda9679b4aa1a3d15fa7a550b48876
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Change-Id: I1ee070291d70b2e30ac2096aa8b3b89e6fcdeff1
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Change-Id: I6bc5fd019160b05f48c9a65639e1025899651f1e
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Change-Id: I6c004836562b0605530ac334434b17afa89ebad5
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This does not scale the EMI frequency and keep the processor
betweel 261MHz and 454MHz. It can still be improve. The auto-slow
divisor could still be change, 8 seems reasonable for now
Change-Id: I639bb3f6b7f8efedc7dc58d08127849156eeb1b6
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Change-Id: Iaaca5caa35b9624d8dd9ea14eabde24c5667e892
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Change-Id: I0f61d0ca8e385fbfeaba53b81c3320b24aa61ab9
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Implemented scheme:
ARM AHB APB
Normal 50 50 50 MHz
Max 200 100 50 MHz
Frequency scaling is disabled on rk27generic due to too
slow lcd updates when running with 50MHz AHB.
battery_bench shows ~1h runtime improvement on hifiman.
Change-Id: I2c6f8acf6d4570c4e14f5bcc72280b51ce13c408
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Change-Id: I798826c8240fa9ce5a87cb0443002ca1b8882922
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Remove the old debug stuff about VDDx and add a clean api to
get/set the regulator (VDDD, VDDA, VDDIO, VDDMEM). This is useful
for proper frequency scaling.
Change-Id: Ia5a1a712fd66652a8ad9601ed00db31aba5a7561
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Change-Id: I1030e94f0dad4b66646cafa20b61df8a5c7f9278
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Change-Id: Ia70a0058f0e86824e2b0d74d12e369295629eb5a
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Due to the way Archos devices (i.e. the only HWCODEC devices) boot,
memory is tight these days. Disabling LOGFDISK on them will make them
work for now. In the long term a better solution is needed.
Change-Id: Ifc6bb97a81cc33545294e319bbc0a6c499788d39
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Change-Id: Ic3f29e75aa5b894f17e289263a370fac13e2f1d8
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Change-Id: Ifc6c25a53ace1a5f4d716a33d4979ea0a37fac98
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Implement cache aligned transfer of more than one sectors. The
current code now transfers almost all data at once by moving
it within the buffer to make it cache aligned. This greatly
improves the performance of the transfers, especially in mass
storage mode.
Change-Id: Ic6e78773302f368426209f6fd6099089ea34cb16
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Change-Id: I7b6bf2bcac31ff65ae17f4a833587f4a5c9e6d7a
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Further merge drivers by using the same command and data functions.
No use one mutex per drive instead of a global sd lock. Fix the
RCA handling which was different between SD and MMC (shifted 16)
and thus confusing. Add MMC commands definition to the mmc.h
header similarly to the SD one. Change MMC handling a bit by
selecting/deselecting on each transfer like SD, which allows
for several MMC devices in theory and is more uniform.
Change-Id: I7024cb19c079553806138ead75b00640f1d2d95c
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Merge sd and mmc drivers into a single sdmmc driver. This allows
some factoring of the code and simplify bug fixing. Also fix the
dma/cache related issue by doing all transfers via a correctly
aligned buffer. The current code is not smart enough to take
advantage of large user buffers currently but at least it is safe!
Change-Id: Ib0fd16dc7d52ef7bfe99fd586e03ecf08691edcd
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There are tricky DMA/cache related issue on the imx233 which could
pop up with the old driver. The new one ensures that all dma
tranfers are cache safe by using an intermediate buffer.
Change-Id: I72060682d1c285c83ae16455cfdb62f372b5d687
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Reduce DMA maximum transfer size since transfering 64Kb requires
to set a size of 0 and it's not worth adding checks everywhere
to handle this special case. Also add statistics about unaligned
transfer (wrt to cache). Update debug screen accordingly and
simplify it so it can fit smaller screens too.
Change-Id: I18391702f5e100a21f6f8d1ebab28d9f2bd8c66f
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Change-Id: I86d6e61a497780a9e22ea16075b055c3d7455630
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Change-Id: I45813d1f34aff74c6b88c84bae6c0feeb4422ed7
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Change-Id: Ida589bcd20227f626349f80293bb423d784519be
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