rockbox - My Rockbox tree

	Commit message (Collapse)	Author	Age
*	hwstub: Add atj213x support	Marcin Bukat	2014-11-05
\| \| \| \|	Change-Id: Ic32200f9ab2c6977e503307a9cbe43a1328d0341
*	atj213x: e100/150 lcd test binary	Marcin Bukat	2014-10-18
\| \| \| \|	Change-Id: I3f9fa21dcb33d1cd3081d0c995adfb44e085dd7a
*	atj213x: various fixes in sample code snippets	Marcin Bukat	2014-03-04
\| \| \| \|	Change-Id: I78781e1a56cb6705d011ee2296f1789b497a566a
*	atj213x: rework crt0.S in test code	Marcin Bukat	2014-02-14
\| \| \| \| \| \| \|	Rework init code so relocation is safe for binaries linked into cached unmapped KSEG0 region. Change-Id: I705ee3f0334f8998237f249a2c3059d6dbe78a43
*	atj213x: Simple test exploring irq handling	Marcin Bukat	2014-02-09
\| \| \| \| \| \| \| \| \|	This test software setups timer T0 periodic interrupt. In ISR it changes backlight level. The interrupt handler does not support nesting and the whole ISR is run in interrupt context. Exceptions are not handled yet. Change-Id: Idc5d622991c7257b4577448d8be08ddd1c24c745
*	adfuload: add atj213x timer0 test program	Marcin Bukat	2014-01-08
\| \| \| \| \| \| \| \| \| \| \|	This simple program shows how to setup timer for periodic operation. Interrupts are not used yet and simply pending irq bit is polled and cleared when set. This program supports my understanding of disassm of ADEC_N63.BIN that P_CLK is configured for 7.5MHz and timer clock source is P_CLK directly. Change-Id: Idd6461bf847c763b78b8c324012ec2515f65dd41
*	atj213x: obtain PC value in more elegant way	Marcin Bukat	2014-01-03
\| \| \| \|	Change-Id: I2e6ffb3b58ddda0ea62ce5d4cd71ac5475b34495
*	adfuload: add test program	Marcin Bukat	2013-12-13
	This test program. I add it mainly to document somehow my work: 1) atj213x.h lists registers addresses 2) crt0.S exploits self relocation of the binary 3) test_bl.c documents how to control backlight on e150 Change-Id: I055e0fe065d926a5c3805b73cea3f537cb64bf52