From 027c035a4e4b24e64bbb4d907f143a208c68675b Mon Sep 17 00:00:00 2001 From: Marcin Bukat Date: Fri, 26 Oct 2012 12:55:13 +0200 Subject: jz4740: a few minor fixes This was spotted while playing with qemu-jz: 1) rockbox reads TECR and TESR which are described as write-only registers. Datasheet doesn't mention what happens if they are readed. Apparently this doesn't have fatal side effects. It comes down to two defines from jz4740.h __tcu_stop_counter(n) and __tcu_start_counter(n) which use read-modify-write sequence. 2) rockbox accesses out of bound offset 0xd4 in DMA memspace. It comes from dis_irq() in system-jz4740.c. NUM_DMA is 6 but DMA channels are 0-5 so (irq <= IRQ_DMA_0 + NUM_DMA)) bound check is wrong. This are *NOT* tested on device. Change-Id: I29dff6a4f828030877b7d50fbcc98866478b9e3d Reviewed-on: http://gerrit.rockbox.org/338 Reviewed-by: Bertrik Sikken Tested-by: Purling Nayuki Reviewed-by: Marcin Bukat --- firmware/export/jz4740.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'firmware/export') diff --git a/firmware/export/jz4740.h b/firmware/export/jz4740.h index 820b43f..379c9f8 100644 --- a/firmware/export/jz4740.h +++ b/firmware/export/jz4740.h @@ -3546,8 +3546,8 @@ static __inline__ void __cpm_select_msc_hs_clk(int sd) #define __tcu_set_pwm_output_shutdown_graceful(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_SD ) #define __tcu_set_pwm_output_shutdown_abrupt(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_SD ) -#define __tcu_start_counter(n) ( REG_TCU_TESR |= (1 << (n)) ) -#define __tcu_stop_counter(n) ( REG_TCU_TECR |= (1 << (n)) ) +#define __tcu_start_counter(n) ( REG_TCU_TESR = (1 << (n)) ) +#define __tcu_stop_counter(n) ( REG_TCU_TECR = (1 << (n)) ) #define __tcu_half_match_flag(n) ( REG_TCU_TFR & (1 << ((n) + 16)) ) #define __tcu_full_match_flag(n) ( REG_TCU_TFR & (1 << (n)) ) -- cgit v1.1