From 780f79e7a4028a57e4bf591539a540dbfae2496d Mon Sep 17 00:00:00 2001 From: Jens Arnold Date: Fri, 10 Nov 2006 20:26:01 +0000 Subject: Removed the Gmini 120 and Gmini SP code. These ports are dead, unfortunately. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@11504 a1c6a512-1295-4272-9138-f99709370657 --- firmware/system.c | 238 +----------------------------------------------------- 1 file changed, 1 insertion(+), 237 deletions(-) (limited to 'firmware/system.c') diff --git a/firmware/system.c b/firmware/system.c index 207a147..102ace6 100644 --- a/firmware/system.c +++ b/firmware/system.c @@ -152,243 +152,7 @@ bool detect_flashed_rockbox(void) #endif /* HAVE_FLASHED_ROCKBOX */ } -#if CONFIG_CPU == TCC730 - -void* volatile interrupt_vector[16] __attribute__ ((section(".idata"))); - -static void ddma_wait_idle(void) __attribute__ ((section (".icode"))); -static void ddma_wait_idle(void) -{ - /* TODO: power saving trick: set the CPU freq to 22MHz - while doing the busy wait after a disk dma access. - (Used by Archos) */ - do { - } while ((DDMACOM & 3) != 0); -} - -void ddma_transfer(int dir, int mem, void* intAddr, long extAddr, int num) - __attribute__ ((section (".icode"))); -void ddma_transfer(int dir, int mem, void* intAddr, long extAddr, int num) { - int irq = set_irq_level(1); - ddma_wait_idle(); - long externalAddress = (long) extAddr; - long internalAddress = ((long) intAddr) & 0xFFFF; - /* HW wants those two in word units. */ - num /= 2; - externalAddress /= 2; - - DDMACFG = (dir << 1) | (mem << 2); - DDMAIADR = internalAddress; - DDMAEADR = externalAddress; - DDMANUM = num; - DDMACOM |= 0x4; /* start */ - - ddma_wait_idle(); /* wait for completion */ - set_irq_level(irq); -} - -static void ddma_wait_idle_noicode(void) -{ - do { - } while ((DDMACOM & 3) != 0); -} - -static void ddma_transfer_noicode(int dir, int mem, long intAddr, long extAddr, int num) { - int irq = set_irq_level(1); - ddma_wait_idle_noicode(); - long externalAddress = (long) extAddr; - long internalAddress = (long) intAddr; - /* HW wants those two in word units. */ - num /= 2; - externalAddress /= 2; - - DDMACFG = (dir << 1) | (mem << 2); - DDMAIADR = internalAddress; - DDMAEADR = externalAddress; - DDMANUM = num; - DDMACOM |= 0x4; /* start */ - - ddma_wait_idle_noicode(); /* wait for completion */ - set_irq_level(irq); -} - -/* Some linker-defined symbols */ -extern int icodecopy; -extern int icodesize; -extern int icodestart; - -/* change the a PLL frequency */ -void set_pll_freq(int pll_index, long freq_out) { - volatile unsigned int* plldata; - volatile unsigned char* pllcon; - if (pll_index == 0) { - plldata = &PLL0DATA; - pllcon = &PLL0CON; - } else { - plldata = &PLL1DATA; - pllcon = &PLL1CON; - } - /* VC0 is 32768 Hz */ -#define VC0FREQ (32768L) - unsigned m = (freq_out / VC0FREQ) - 2; - /* TODO: if m is too small here, use the divider bits [0,1] */ - *plldata = m << 2; - *pllcon |= 0x1; /* activate */ - do { - } while ((*pllcon & 0x2) == 0); /* wait for stabilization */ -} - -int smsc_version(void) { - int v; - int* smsc_ver_addr = (int*)0x4C20; - __asm__ ("ldc %0, @%1" : "=r"(v) : "a"(smsc_ver_addr)); - v &= 0xFF; - if (v < 4 || v == 0xFF) { - return 3; - } - return v; -} - - - -void smsc_delay() { - int i; - /* FIXME: tune the delay. - Delay doesn't depend on CPU speed in Archos' firmware. - */ - for (i = 0; i < 100; i++) { - - } -} - -static void extra_init(void) { - /* Power on stuff */ - P1 |= 0x07; - P1CON |= 0x1f; - - /* P5 conf - * lines 0, 1 & 4 are digital, other analog. : - */ - P5CON = 0xec; - - P6CON = 0x19; - - /* P7 conf - nothing to do: all are inputs - (reset value of the register is good) - */ - - /* SMSC chip config (?) */ - P10CON |= 0x20; - P6 &= 0xF7; - P10 &= 0x20; - smsc_delay(); - if (smsc_version() < 4) { - P6 |= 0x08; - P10 |= 0x20; - } -} - -void set_cpu_frequency(long frequency) { - /* Enable SDRAM refresh, at least 15MHz */ - if (frequency < cpu_frequency) - MIUDCNT = 0x800 | (frequency * 15/1000000L - 1); - - set_pll_freq(0, frequency); - PLL0CON |= 0x4; /* use as CPU clock */ - - cpu_frequency = frequency; - /* wait states and such not changed by Archos. (!?) */ - - /* Enable SDRAM refresh, 15MHz. */ - MIUDCNT = 0x800 | (frequency * 15/1000000L - 1); - - tick_start(1000/HZ); - /* TODO: when uart is done; sync uart freq */ -} - -/* called by crt0 */ -void system_init(void) -{ - /* Disable watchdog */ - WDTEN = 0xA5; - - /**************** - * GPIO ports - */ - - /* keep alive (?) -- clear the bit to prevent crash at start (??) */ - P8 = 0x00; - P8CON = 0x01; - - /* smsc chip init (?) */ - P10 = 0x20; - P6 = 0x08; - - P10CON = 0x20; - P6CON = 0x08; - - /******** - * CPU - */ - - - /* PLL0 (cpu osc. frequency) */ - /* set_cpu_frequency(CPU_FREQ); */ - - - /******************* - * configure S(D)RAM - */ - - /************************ - * Copy .icode section to icram - */ - ddma_transfer_noicode(0, 0, 0x40, (long)&icodecopy, (int)&icodesize); - - - /*************************** - * Interrupts - */ - - /* priorities ? */ - - /* mask */ - IMR0 = 0; - IMR1 = 0; - - -/* IRQ0 BT INT */ -/* IRQ1 RTC INT */ -/* IRQ2 TA INT */ -/* IRQ3 TAOV INT */ -/* IRQ4 TB INT */ -/* IRQ5 TBOV INT */ -/* IRQ6 TC INT */ -/* IRQ7 TCOV INT */ -/* IRQ8 USB INT */ -/* IRQ9 PPIC INT */ -/* IRQ10 UART_Rx/UART_Err/ UART_tx INT */ -/* IRQ11 IIC INT */ -/* IRQ12 SIO INT */ -/* IRQ13 IIS0 INT */ -/* IRQ14 IIS1 INT */ -/* IRQ15 */ - - extra_init(); -} - -void system_reboot (void) -{ -} - -int system_memory_guard(int newmode) -{ - (void)newmode; - return 0; -} - -#elif CONFIG_CPU == SH7034 +#if CONFIG_CPU == SH7034 #include "led.h" #include "system.h" #include "rolo.h" -- cgit v1.1