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authorLinus Nielsen Feltzing <linus@haxx.se>2006-10-12 20:22:16 +0000
committerLinus Nielsen Feltzing <linus@haxx.se>2006-10-12 20:22:16 +0000
commit00d218257be50f7f572deeed49f2ba9b2e235834 (patch)
treed3cbe8630aaebbd0ff4c3986b826e1494180f2c5
parenta60bb9a067ba36866eba176bcc654619dea66bb2 (diff)
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Logf output on the serial port for h100 targets
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@11207 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r--firmware/drivers/serial.c26
-rw-r--r--firmware/export/config-h120.h3
-rw-r--r--firmware/export/serial.h1
-rw-r--r--firmware/logf.c5
-rw-r--r--firmware/system.c22
5 files changed, 56 insertions, 1 deletions
diff --git a/firmware/drivers/serial.c b/firmware/drivers/serial.c
index 46280bc..5120161 100644
--- a/firmware/drivers/serial.c
+++ b/firmware/drivers/serial.c
@@ -143,7 +143,31 @@ int remote_control_rx(void)
}
#endif /* HAVE_MMC */
-#else /* (CONFIG_CPU != MCF5249) && (CONFIG_CPU != TCC730) */
+#elif defined(CPU_COLDFIRE) && defined(HAVE_SERIAL)
+
+void serial_tx(const unsigned char *buf)
+{
+ while(*buf) {
+ while(!(USR0 & 0x04))
+ {
+ };
+ UTB0 = *buf++;
+ }
+}
+
+void serial_setup (void)
+{
+ UCR0 = 0x30; /* Reset transmitter */
+ UCSR0 = 0xdd; /* Timer mode */
+
+ UCR0 = 0x10; /* Reset pointer */
+ UMR0 = 0x13; /* No parity, 8 bits */
+ UMR0 = 0x07; /* 1 stop bit */
+
+ UCR0 = 0x04; /* Tx enable */
+}
+
+#else /* Other targets */
void serial_setup (void)
{
/* a dummy */
diff --git a/firmware/export/config-h120.h b/firmware/export/config-h120.h
index e6aa822..d8038f2 100644
--- a/firmware/export/config-h120.h
+++ b/firmware/export/config-h120.h
@@ -150,3 +150,6 @@
/* Define this for FM radio input available */
#define HAVE_FMRADIO_IN
+
+/* Define this if you have a serial port */
+/*#define HAVE_SERIAL*/
diff --git a/firmware/export/serial.h b/firmware/export/serial.h
index f2e5a94..add6cc8 100644
--- a/firmware/export/serial.h
+++ b/firmware/export/serial.h
@@ -22,5 +22,6 @@
extern void serial_setup (void);
extern int remote_control_rx(void);
+extern void serial_tx(const unsigned char *buf);
#endif
diff --git a/firmware/logf.c b/firmware/logf.c
index f61797b..fc57bd8 100644
--- a/firmware/logf.c
+++ b/firmware/logf.c
@@ -31,6 +31,7 @@
#include "config.h"
#include "lcd-remote.h"
#include "logf.h"
+#include "serial.h"
/* Only provide all this if asked to */
#ifdef ROCKBOX_HAS_LOGF
@@ -90,6 +91,10 @@ void logf(const char *format, ...)
}
ptr = logfbuffer[logfindex];
len = vsnprintf(ptr, MAX_LOGF_ENTRY, format, ap);
+#ifdef HAVE_SERIAL
+ serial_tx(ptr);
+ serial_tx("\r\n");
+#endif
va_end(ap);
if(len < MAX_LOGF_ENTRY)
/* pad with spaces up to the MAX_LOGF_ENTRY byte border */
diff --git a/firmware/system.c b/firmware/system.c
index 655b08d..c597fc5 100644
--- a/firmware/system.c
+++ b/firmware/system.c
@@ -685,6 +685,13 @@ int system_memory_guard(int newmode)
#define RECALC_DELAYS(f)
#endif
+#ifdef HAVE_SERIAL
+#define BAUD_RATE 57600
+#define BAUDRATE_DIV_DEFAULT (CPUFREQ_DEFAULT/(BAUD_RATE*32*2))
+#define BAUDRATE_DIV_NORMAL (CPUFREQ_NORMAL/(BAUD_RATE*32*2))
+#define BAUDRATE_DIV_MAX (CPUFREQ_MAX/(BAUD_RATE*32*2))
+#endif
+
void set_cpu_frequency (long) __attribute__ ((section (".icode")));
void set_cpu_frequency(long frequency)
{
@@ -710,6 +717,11 @@ void set_cpu_frequency(long frequency)
IDECONFIG1 = 0x10100000 | (1 << 13) | (2 << 10);
/* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */
IDECONFIG2 = 0x40000 | (2 << 8); /* TA enable + CS2wait */
+
+#ifdef HAVE_SERIAL
+ UBG10 = BAUDRATE_DIV_MAX >> 8;
+ UBG20 = BAUDRATE_DIV_MAX & 0xff;
+#endif
break;
case CPUFREQ_NORMAL:
@@ -732,6 +744,11 @@ void set_cpu_frequency(long frequency)
IDECONFIG1 = 0x10100000 | (0 << 13) | (1 << 10);
/* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */
IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */
+
+#ifdef HAVE_SERIAL
+ UBG10 = BAUDRATE_DIV_NORMAL >> 8;
+ UBG20 = BAUDRATE_DIV_NORMAL & 0xff;
+#endif
break;
default:
DCR = (DCR & ~0x01ff) | DEFAULT_REFRESH_TIMER;
@@ -750,6 +767,11 @@ void set_cpu_frequency(long frequency)
IDECONFIG1 = 0x10100000 | (0 << 13) | (1 << 10);
/* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */
IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */
+
+#ifdef HAVE_SERIAL
+ UBG10 = BAUDRATE_DIV_DEFAULT >> 8;
+ UBG20 = BAUDRATE_DIV_DEFAULT & 0xff;
+#endif
break;
}
}