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| author | Amaury Pouly <amaury.pouly@gmail.com> | 2013-01-10 01:02:12 +0000 |
|---|---|---|
| committer | Amaury Pouly <amaury.pouly@gmail.com> | 2013-01-10 01:02:12 +0000 |
| commit | 1fa406dc216cbbabd9f17df6312abf205976276f (patch) | |
| tree | 576960251e968e706cc978d6f11c94baf5c62fef | |
| parent | 5aa19f3eeb4e401b2d1ac57131a87b87b6ce55d5 (diff) | |
| download | rockbox-1fa406dc216cbbabd9f17df6312abf205976276f.zip rockbox-1fa406dc216cbbabd9f17df6312abf205976276f.tar.gz rockbox-1fa406dc216cbbabd9f17df6312abf205976276f.tar.bz2 rockbox-1fa406dc216cbbabd9f17df6312abf205976276f.tar.xz | |
imx233: modify arm cache timings on frequency switch
The manual recommands to tweak the arm cache settings on frequency
changes. The meaning of these values is undocumented but 0 seems
to be a safe value for all frequencies whereas 3 seems to be valid
only for low frequencies (<=64MHz ?)
Change-Id: Iaa8db4af8191010789cf986b1139ff259d73e2ed
| -rw-r--r-- | firmware/target/arm/imx233/system-imx233.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/system-imx233.c b/firmware/target/arm/imx233/system-imx233.c index 68f0635..dfa6b56 100644 --- a/firmware/target/arm/imx233/system-imx233.c +++ b/firmware/target/arm/imx233/system-imx233.c @@ -163,6 +163,16 @@ void udelay(unsigned us) while(!imx233_us_elapsed(ref, us)); } +void imx233_digctl_set_arm_cache_timings(unsigned timings) +{ + HW_DIGCTL_ARMCACHE = + timings << HW_DIGCTL_ARMCACHE__ITAG_SS_BP | + timings << HW_DIGCTL_ARMCACHE__DTAG_SS_BP | + timings << HW_DIGCTL_ARMCACHE__CACHE_SS_BP | + timings << HW_DIGCTL_ARMCACHE__DRTY_SS_BP | + timings << HW_DIGCTL_ARMCACHE__VALID_SS_BP; +} + #ifdef HAVE_ADJUSTABLE_CPU_FREQ void set_cpu_frequency(long frequency) { @@ -185,6 +195,7 @@ void set_cpu_frequency(long frequency) * changes are safe too */ imx233_clkctrl_set_clock_divisor(CLK_HBUS, 4); imx233_clkctrl_set_bypass_pll(CLK_CPU, true); + imx233_digctl_set_arm_cache_timings(0); switch(frequency) { @@ -233,6 +244,7 @@ void set_cpu_frequency(long frequency) imx233_clkctrl_set_bypass_pll(CLK_CPU, false); imx233_emi_set_frequency(IMX233_EMIFREQ_64_MHz); + imx233_digctl_set_arm_cache_timings(3); /* ref_cpu@480 MHz * ref_emi@480 MHz * clk_emi@64 MHz |