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| author | Amaury Pouly <amaury.pouly@gmail.com> | 2013-07-02 00:31:57 +0200 |
|---|---|---|
| committer | Amaury Pouly <amaury.pouly@gmail.com> | 2013-07-02 00:45:00 +0200 |
| commit | 277367373300bc4bb034f0ef57809989eeb2d233 (patch) | |
| tree | e6d42a3030e5b5e207fa69e99b2e4fa4c06a4c33 | |
| parent | bb87590e05f6e5c3839bcebe84fb221396905294 (diff) | |
| download | rockbox-277367373300bc4bb034f0ef57809989eeb2d233.zip rockbox-277367373300bc4bb034f0ef57809989eeb2d233.tar.gz rockbox-277367373300bc4bb034f0ef57809989eeb2d233.tar.bz2 rockbox-277367373300bc4bb034f0ef57809989eeb2d233.tar.xz | |
imx233: fix emi frequency scaling
On the ZEN X-Fi2, the fractiona dividers are gated by the
bootloader and must be ungated before switching emi to pll.
Change-Id: I5df57ed5581054883da4cbb3b4f3ce3539391ab5
| -rw-r--r-- | firmware/target/arm/imx233/emi-imx233.c | 2 | ||||
| -rw-r--r-- | firmware/target/arm/imx233/system-imx233.c | 6 |
2 files changed, 5 insertions, 3 deletions
diff --git a/firmware/target/arm/imx233/emi-imx233.c b/firmware/target/arm/imx233/emi-imx233.c index d69dc4a..c62fa58 100644 --- a/firmware/target/arm/imx233/emi-imx233.c +++ b/firmware/target/arm/imx233/emi-imx233.c @@ -121,7 +121,9 @@ static void set_frequency(unsigned long freq) * clk_emi@64 MHz */ break; } + BF_WR(CLKCTRL_FRAC, CLKGATEEMI, 0); BF_WR(CLKCTRL_FRAC, EMIFRAC, fracdiv); + BF_WR(CLKCTRL_EMI, CLKGATE, 0); BF_WR(CLKCTRL_EMI, DIV_EMI, div); } diff --git a/firmware/target/arm/imx233/system-imx233.c b/firmware/target/arm/imx233/system-imx233.c index 9a8ff61..aa1c216 100644 --- a/firmware/target/arm/imx233/system-imx233.c +++ b/firmware/target/arm/imx233/system-imx233.c @@ -200,11 +200,11 @@ struct cpufreq_profile_t static struct cpufreq_profile_t cpu_profiles[] = { - /* clk_p@454.74 MHz, clk_h@130.91 MHz, clk_emi@130.91 MHz */ + /* clk_p@454.74 MHz, clk_h@130.91 MHz, clk_emi@130.91 MHz, VDDD@1.550 V */ {IMX233_CPUFREQ_454_MHz, 1550, 1450, 3, 1, 19, IMX233_EMIFREQ_130_MHz, 0}, - /* clk_p@261.82 MHz, clk_h@130.91 MHz, clk_emi@130.91 MHz */ + /* clk_p@261.82 MHz, clk_h@130.91 MHz, clk_emi@130.91 MHz, VDDD@1.275 V */ {IMX233_CPUFREQ_261_MHz, 1275, 1175, 2, 1, 33, IMX233_EMIFREQ_130_MHz, 0}, - /* clk_p@64 MHz, clk_h@64 MHz, clk_emi@64 MHz */ + /* clk_p@64 MHz, clk_h@64 MHz, clk_emi@64 MHz, VDDD@1.050 V */ {IMX233_CPUFREQ_64_MHz, 1050, 975, 1, 5, 27, IMX233_EMIFREQ_64_MHz, 0}, /* dummy */ {0, 0, 0, 0, 0, 0, 0, 0} |