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authorBertrik Sikken <bertrik@sikken.nl>2009-05-21 18:31:50 +0000
committerBertrik Sikken <bertrik@sikken.nl>2009-05-21 18:31:50 +0000
commit4a4639e157762bacfe84a99a91feabf282b5546f (patch)
tree45be6c581efdc8e3bae916d8d3a69f1e54607085
parent442726339ab0a424edf0e3406c68faacb425d9a2 (diff)
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Update as3525 i2c register description
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21018 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r--firmware/target/arm/as3525/ascodec-as3525.c9
1 files changed, 8 insertions, 1 deletions
diff --git a/firmware/target/arm/as3525/ascodec-as3525.c b/firmware/target/arm/as3525/ascodec-as3525.c
index 43a982f..b979021 100644
--- a/firmware/target/arm/as3525/ascodec-as3525.c
+++ b/firmware/target/arm/as3525/ascodec-as3525.c
@@ -27,7 +27,14 @@
I2C register description:
* I2C2_CNTRL needs to be set to 0x51 for transfers to work at all.
- bit 1 indicates direction of transfer (0 = write, 1 = read)
+ bit 0: ? possibly related to using ACKs during transfers
+ bit 1: direction of transfer (0 = write, 1 = read)
+ bit 2: use 2-byte slave address
+ * I2C2_IMR, I2C2_RIS, I2C2_MIS, I2C2_INT_CLR interrupt bits:
+ bit 2: byte read interrupt
+ bit 3: byte write interrupt
+ bit 4: ? possibly some kind of error status
+ bit 7: ACK error
* I2C2_SR (status register) indicates in bit 0 if a transfer is busy.
* I2C2_SLAD0 contains the i2c slave address to read from / write to.
* I2C2_CPSR0/1 is the divider from the peripheral clock to the i2c clock.