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| author | Rafaël Carré <rafael.carre@gmail.com> | 2008-12-01 04:07:13 +0000 |
|---|---|---|
| committer | Rafaël Carré <rafael.carre@gmail.com> | 2008-12-01 04:07:13 +0000 |
| commit | 50519416ca1c591f16fd4c59107e9c10eb4e2380 (patch) | |
| tree | cb6207b0804717d99594864eafabfa8f8ca491a0 | |
| parent | c9ba3adf0ddef0ce55dd24e446b878e3de9ee058 (diff) | |
| download | rockbox-50519416ca1c591f16fd4c59107e9c10eb4e2380.zip rockbox-50519416ca1c591f16fd4c59107e9c10eb4e2380.tar.gz rockbox-50519416ca1c591f16fd4c59107e9c10eb4e2380.tar.bz2 rockbox-50519416ca1c591f16fd4c59107e9c10eb4e2380.tar.xz | |
Sansa Clip : save one instruction per 8 pixels loop in lcd_grey_data
We set directly the needed bits to write into DBOP_DOUT (15:13 and 3:0)
Since we can't set the mask 0xf00f with one mov instruction, revert the
logic and use orrne instead of biceq (in the whole function for consistency)
Fix suggested by Jens Arnold
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19279 a1c6a512-1295-4272-9138-f99709370657
| -rw-r--r-- | firmware/target/arm/as3525/sansa-clip/lcd-as-clip.S | 22 |
1 files changed, 12 insertions, 10 deletions
diff --git a/firmware/target/arm/as3525/sansa-clip/lcd-as-clip.S b/firmware/target/arm/as3525/sansa-clip/lcd-as-clip.S index aab4686..0f68a2f 100644 --- a/firmware/target/arm/as3525/sansa-clip/lcd-as-clip.S +++ b/firmware/target/arm/as3525/sansa-clip/lcd-as-clip.S @@ -59,32 +59,34 @@ lcd_grey_data: ldmia r1, {r3-r4} /* Fetch 8 pixel phases */ ldmia r0!, {r5-r6} /* Fetch 8 pixel values */ - mov r7, #0xff + mov r7, #0 + + /* set bits 15..12 */ tst r3, #0x80 - biceq r7, r7, #0x80 + orrne r7, r7, #0x8000 tst r3, #0x8000 - biceq r7, r7, #0x40 + orrne r7, r7, #0x4000 tst r3, #0x800000 - biceq r7, r7, #0x20 + orrne r7, r7, #0x2000 tst r3, #0x80000000 - biceq r7, r7, #0x10 + orrne r7, r7, #0x1000 bic r3, r3, r8 add r3, r3, r5 + /* set bits 3..0 */ tst r4, #0x80 - biceq r7, r7, #0x08 + orrne r7, r7, #0x08 tst r4, #0x8000 - biceq r7, r7, #0x04 + orrne r7, r7, #0x04 tst r4, #0x800000 - biceq r7, r7, #0x02 + orrne r7, r7, #0x02 tst r4, #0x80000000 - biceq r7, r7, #0x01 + orrne r7, r7, #0x01 bic r4, r4, r8 add r4, r4, r6 stmia r1!, {r3-r4} - orr r7, r7, r7, lsl #8 @ we set 15:13 to the MSb and 3:0 to the LSb strh r7, [lr, #0x10] @ DBOP_DOUT 1: |