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| author | Linus Nielsen Feltzing <linus@haxx.se> | 2002-05-05 22:14:07 +0000 |
|---|---|---|
| committer | Linus Nielsen Feltzing <linus@haxx.se> | 2002-05-05 22:14:07 +0000 |
| commit | 551d8368aa95f91de33ce07a6722705542f77e3a (patch) | |
| tree | 5bebe5c9baa8620d51e53936cda39854440bea93 | |
| parent | 55fec178bc630e3a52f46bcd74bc1bf319a1bc1a (diff) | |
| download | rockbox-551d8368aa95f91de33ce07a6722705542f77e3a.zip rockbox-551d8368aa95f91de33ce07a6722705542f77e3a.tar.gz rockbox-551d8368aa95f91de33ce07a6722705542f77e3a.tar.bz2 rockbox-551d8368aa95f91de33ce07a6722705542f77e3a.tar.xz | |
corrected a few errors
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@454 a1c6a512-1295-4272-9138-f99709370657
| -rw-r--r-- | firmware/drivers/sh7034.h | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/firmware/drivers/sh7034.h b/firmware/drivers/sh7034.h index 6d6fb6d..bd89412 100644 --- a/firmware/drivers/sh7034.h +++ b/firmware/drivers/sh7034.h @@ -95,20 +95,20 @@ #define SAR0_ADDR 0x05FFFF40 #define DAR0_ADDR 0x05FFFF44 -#define OR_ADDR 0x05FFFF48 -#define DTCR0_ADDR 0x05FFFF4A +#define DMAOR_ADDR 0x05FFFF48 +#define DTCR0_ADDR 0x05FFFF4A #define CHCR0_ADDR 0x05FFFF4E #define SAR1_ADDR 0x05FFFF50 #define DAR1_ADDR 0x05FFFF54 -#define DTCR1_ADDR 0x05FFFF5A +#define DTCR1_ADDR 0x05FFFF5A #define CHCR1_ADDR 0x05FFFF5E #define SAR2_ADDR 0x05FFFF60 #define DAR2_ADDR 0x05FFFF64 -#define DTCR2_ADDR 0x05FFFF6A +#define DTCR2_ADDR 0x05FFFF6A #define CHCR2_ADDR 0x05FFFF6E #define SAR3_ADDR 0x05FFFF70 #define DAR3_ADDR 0x05FFFF74 -#define DTCR3_ADDR 0x05FFFF7A +#define DTCR3_ADDR 0x05FFFF7A #define CHCR3_ADDR 0x05FFFF7E #define IPRA_ADDR 0x05FFFF84 @@ -231,20 +231,20 @@ #define SAR0 (*((volatile unsigned long*)SAR0_ADDR)) #define DAR0 (*((volatile unsigned long*)DAR0_ADDR)) -#define DMAOR (*((volatile unsigned long*)DMAOR_ADDR)) -#define DTCR0 (*((volatile unsigned long*)DTCR0_ADDR)) +#define DMAOR (*((volatile unsigned short*)DMAOR_ADDR)) +#define DTCR0 (*((volatile unsigned short*)DTCR0_ADDR)) #define CHCR0 (*((volatile unsigned short*)CHCR0_ADDR)) #define SAR1 (*((volatile unsigned long*)SAR1_ADDR)) #define DAR1 (*((volatile unsigned long*)DAR1_ADDR)) -#define DTCR1 (*((volatile unsigned long*)DTCR1_ADDR)) +#define DTCR1 (*((volatile unsigned short*)DTCR1_ADDR)) #define CHCR1 (*((volatile unsigned short*)CHCR1_ADDR)) #define SAR2 (*((volatile unsigned long*)SAR2_ADDR)) #define DAR2 (*((volatile unsigned long*)DAR2_ADDR)) -#define DTCR2 (*((volatile unsigned long*)DTCR2_ADDR)) +#define DTCR2 (*((volatile unsigned short*)DTCR2_ADDR)) #define HCR2 (*((volatile unsigned short*)CHCR2_ADDR)) #define SAR3 (*((volatile unsigned long*)SAR3_ADDR)) #define DAR3 (*((volatile unsigned long*)DAR3_ADDR)) -#define DTCR3 (*((volatile unsigned long*)DTCR3_ADDR)) +#define DTCR3 (*((volatile unsigned short*)DTCR3_ADDR)) #define CHCR3 (*((volatile unsigned short*)CHCR3_ADDR)) #define IPRA (*((volatile unsigned short*)IPRA_ADDR)) |