iPod 1st..3rd gen: Fix CPU scaling instability on PP5002 * Add some new info to pp5002.h and sort it by port address.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14053 a1c6a512-1295-4272-9138-f99709370657

3 files changed, 95 insertions, 90 deletions

diff --git a/apps/debug_menu.c b/apps/debug_menu.c
index d1e1b86..aaac255 100644
--- a/apps/debug_menu.c
+++ b/apps/debug_menu.c
@@ -1278,7 +1278,7 @@ bool dbg_ports(void)
         lcd_puts(0, line++, buf);
         snprintf(buf, sizeof(buf), "CLOCK_SOURCE: %08lx", CLOCK_SOURCE);
         lcd_puts(0, line++, buf);
-        snprintf(buf, sizeof(buf), "CLOCK_DIV:    %08lx", CLOCK_DIV);
+        snprintf(buf, sizeof(buf), "PLL_CONTROL:  %08lx", PLL_CONTROL);
         lcd_puts(0, line++, buf);
         snprintf(buf, sizeof(buf), "PLL_DIV:      %08lx", PLL_DIV);
         lcd_puts(0, line++, buf);
diff --git a/firmware/export/pp5002.h b/firmware/export/pp5002.h
index 0610da8..f2a7630 100644
--- a/firmware/export/pp5002.h
+++ b/firmware/export/pp5002.h
@@ -19,13 +19,24 @@
 #ifndef __PP5002_H__
 #define __PP5002_H__
 
-/* All info gleaned and/or copied from the iPodLinux project. */
+/* Much info gleaned and/or copied from the iPodLinux project. */
 #define DRAM_START       0x28000000
 
 #define IPOD_LCD_BASE    0xc0001000
 
-#define CPU_CTL          (*(volatile unsigned char *)(0xcf004054))
-#define COP_CTL          (*(volatile unsigned char *)(0xcf004058))
+#define IISCONFIG        (*(volatile unsigned long *)(0xc0002500))
+
+#define IISFIFO_CFG      (*(volatile unsigned long *)(0xc000251c))
+#define IISFIFO_WR       (*(volatile unsigned long *)(0xc0002540))
+#define IISFIFO_RD       (*(volatile unsigned long *)(0xc0002580))
+
+#define I2C_BASE         0xc0008000
+
+/* The PortalPlayer USB controller uses base address 0xc5000000 */
+#define USB_BASE         0xc5000000
+
+#define USB2D_IDENT      (*(volatile unsigned long *)(0xc5000000))
+#define USB_STATUS       (*(volatile unsigned long *)(0xc50001a4))
 
 #define GPIOA_ENABLE     (*(volatile unsigned char *)(0xcf000000))
 #define GPIOB_ENABLE     (*(volatile unsigned char *)(0xcf000004))
@@ -60,84 +71,78 @@
 #define GPIOC_INT_CLR    (*(volatile unsigned char *)(0xcf000078))
 #define GPIOD_INT_CLR    (*(volatile unsigned char *)(0xcf00007c))
 
-#define DEV_RS (*(volatile unsigned long *)( 0xcf005030))
-#define DEV_EN (*(volatile unsigned long *)( 0xcf005000))
-
-#define DEV_I2C     (1<<8)
-#define DEV_USB     0x400000
+#define INT_FORCED_CLR   (*(volatile unsigned long *)(0xcf00101c))
+#define CPU_INT_STAT     (*(volatile unsigned long *)(0xcf001000))
+#define CPU_INT_EN       (*(volatile unsigned long *)(0xcf001024))
+#define CPU_INT_CLR      (*(volatile unsigned long *)(0xcf001028))
+#define CPU_INT_PRIORITY (*(volatile unsigned long *)(0xcf00102c))
+#define COP_INT_STAT     (*(volatile unsigned long *)(0xcf001010))
+#define COP_INT_EN       (*(volatile unsigned long *)(0xcf001034))
+#define COP_INT_CLR      (*(volatile unsigned long *)(0xcf001038))
+#define COP_INT_PRIORITY (*(volatile unsigned long *)(0xcf00103c))
 
-#define DEV_INIT    (*(volatile unsigned long *)(0x70000020))
+#define IDE_IRQ          1
+#define SER0_IRQ         4
+#define I2S_IRQ          5
+#define SER1_IRQ         7
+#define TIMER1_IRQ      11
+#define TIMER2_IRQ      12
+#define GPIO_IRQ        14
+#define DMA_OUT_IRQ     30
+#define DMA_IN_IRQ      31
 
-#define INIT_USB    0x80000000
+#define IDE_MASK         (1 << IDE_IRQ)
+#define SER0_MASK        (1 << SER0_IRQ)
+#define I2S_MASK         (1 << I2S_IRQ)
+#define SER1_MASK        (1 << SER1_IRQ)
+#define TIMER1_MASK      (1 << TIMER1_IRQ)
+#define TIMER2_MASK      (1 << TIMER2_IRQ)
+#define GPIO_MASK        (1 << GPIO_IRQ)
+#define DMA_OUT_MASK     (1 << DMA_OUT_IRQ)
+#define DMA_IN_MASK      (1 << DMA_IN_IRQ)
 
-#define CPU_INT_STAT     (*(volatile unsigned long*)(0xcf001000))
-#define CPU_INT_EN       (*(volatile unsigned long*)(0xcf001024))
-#define CPU_INT_CLR      (*(volatile unsigned long*)(0xcf001028))
-#define COP_INT_STAT     (*(volatile unsigned long*)(0xcf001010)) /* A guess */
-#define COP_INT_EN       (*(volatile unsigned long*)(0xcf001034))
-#define COP_INT_CLR      (*(volatile unsigned long*)(0xcf001038))
 
-#define USB2D_IDENT         (*(volatile unsigned long*)(0xc5000000))
-#define USB_STATUS          (*(volatile unsigned long*)(0xc50001a4))
+#define TIMER1_CFG       (*(volatile unsigned long *)(0xcf001100))
+#define TIMER1_VAL       (*(volatile unsigned long *)(0xcf001104))
+#define TIMER2_CFG       (*(volatile unsigned long *)(0xcf001108))
+#define TIMER2_VAL       (*(volatile unsigned long *)(0xcf00110c))
 
-#define IISCONFIG           (*(volatile unsigned long*)(0xc0002500))
+#define USEC_TIMER       (*(volatile unsigned long *)(0xcf001110))
 
-#define IISFIFO_CFG         (*(volatile unsigned long*)(0xc000251c))
-#define IISFIFO_WR          (*(volatile unsigned long*)(0xc0002540))
-#define IISFIFO_RD          (*(volatile unsigned long*)(0xc0002580))
+#define TIMING1_CTL      (*(volatile unsigned long *)(0xcf004000))
+#define TIMING2_CTL      (*(volatile unsigned long *)(0xcf004008))
 
-#define I2C_BASE     0xc0008000
+#define CPU_CTL          (*(volatile unsigned char *)(0xcf004054))
+#define COP_CTL          (*(volatile unsigned char *)(0xcf004058))
 
-#define TIMER1_CFG   (*(volatile unsigned long *)(0xcf001100))
-#define TIMER1_VAL   (*(volatile unsigned long *)(0xcf001104))
-#define TIMER2_CFG   (*(volatile unsigned long *)(0xcf001108))
-#define TIMER2_VAL   (*(volatile unsigned long *)(0xcf00110c))
+#define PROC_SLEEP       0xca
+#define PROC_WAKE        0xce
 
-#define USEC_TIMER   (*(volatile unsigned long *)(0xcf001110))
 
-#define PP5002_TIMER_STATUS 0xcf001110
+#define DEV_EN           (*(volatile unsigned long *)(0xcf005000))
+#define DEV_RS           (*(volatile unsigned long *)(0xcf005030))
 
-#define IDE_IRQ          1
-#define SER0_IRQ         4
-#define I2S_IRQ          5
-#define SER1_IRQ         7
-#define TIMER1_IRQ      11
-#define TIMER2_IRQ      12 /* NOTE: THIS IS A GUESS, NEEDS TESTING */
-#define GPIO_IRQ        14
-#define DMA_OUT_IRQ     30
-#define DMA_IN_IRQ      31
+#define DEV_I2C          (1<<8)
+#define DEV_USB          0x400000
 
-#define TIMER1_MASK  (1 << TIMER1_IRQ)
-#define TIMER2_MASK  (1 << TIMER2_IRQ)
-#define I2S_MASK     (1 << I2S_IRQ)
-#define IDE_MASK     (1 << IDE_IRQ)
-#define GPIO_MASK    (1 << GPIO_IRQ)
-#define SER0_MASK    (1 << SER0_IRQ)
-#define SER1_MASK    (1 << SER1_IRQ)
-#define DMA_OUT_MASK (1 << DMA_OUT_IRQ)
-
-#define TIMING1_CTL         (*(volatile unsigned long*)(0xcf004000))
-#define TIMING2_CTL         (*(volatile unsigned long*)(0xcf004008))
-
-#define CLOCK_ENABLE        (*(volatile unsigned long*)(0xcf005008))
-#define CLOCK_SOURCE        (*(volatile unsigned long*)(0xcf00500c))
-#define CLOCK_DIV           (*(volatile unsigned long*)(0xcf005010))
-#define PLL_DIV             (*(volatile unsigned long*)(0xcf005018))
-#define PLL_MULT            (*(volatile unsigned long*)(0xcf00501c))
-
-#define MMAP0_LOGICAL       (*(volatile unsigned long*)(0xf000f000))
-#define MMAP0_PHYSICAL      (*(volatile unsigned long*)(0xf000f004))
-#define MMAP1_LOGICAL       (*(volatile unsigned long*)(0xf000f008))
-#define MMAP1_PHYSICAL      (*(volatile unsigned long*)(0xf000f00c))
-#define MMAP2_LOGICAL       (*(volatile unsigned long*)(0xf000f010))
-#define MMAP2_PHYSICAL      (*(volatile unsigned long*)(0xf000f014))
-#define MMAP3_LOGICAL       (*(volatile unsigned long*)(0xf000f018))
-#define MMAP3_PHYSICAL      (*(volatile unsigned long*)(0xf000f01c))
+#define CLOCK_ENABLE     (*(volatile unsigned long *)(0xcf005008))
+#define CLOCK_SOURCE     (*(volatile unsigned long *)(0xcf00500c))
+#define PLL_CONTROL      (*(volatile unsigned long *)(0xcf005010))
+#define PLL_DIV          (*(volatile unsigned long *)(0xcf005018))
+#define PLL_MULT         (*(volatile unsigned long *)(0xcf00501c))
 
-/* The PortalPlayer USB controller uses base address 0xc5000000 */
-#define USB_BASE                0xc5000000
+#define MMAP0_LOGICAL    (*(volatile unsigned long *)(0xf000f000))
+#define MMAP0_PHYSICAL   (*(volatile unsigned long *)(0xf000f004))
+#define MMAP1_LOGICAL    (*(volatile unsigned long *)(0xf000f008))
+#define MMAP1_PHYSICAL   (*(volatile unsigned long *)(0xf000f00c))
+#define MMAP2_LOGICAL    (*(volatile unsigned long *)(0xf000f010))
+#define MMAP2_PHYSICAL   (*(volatile unsigned long *)(0xf000f014))
+#define MMAP3_LOGICAL    (*(volatile unsigned long *)(0xf000f018))
+#define MMAP3_PHYSICAL   (*(volatile unsigned long *)(0xf000f01c))
 
-#define PROC_SLEEP   0xca
-#define PROC_WAKE    0xce
+/* FIXME: These are PP502x definitions, but without them, iPod 3rd gen
+ * doesn't compile. The correct values for 3rd gen are not yet known. */
+#define DEV_INIT    (*(volatile unsigned long *)(0x70000020))
+#define INIT_USB    0x80000000
 
 #endif
diff --git a/firmware/target/arm/system-pp5002.c b/firmware/target/arm/system-pp5002.c
index 8ed6592..716422a 100644
--- a/firmware/target/arm/system-pp5002.c
+++ b/firmware/target/arm/system-pp5002.c
@@ -96,40 +96,34 @@ void set_cpu_frequency(long frequency)
         cpu_frequency = frequency;
 
         outl(0xd19b, 0xcf005038);
-        outl(0x02, 0xcf005008);
-        outl(0x55, 0xcf00500c);
-        outl(0x6000, 0xcf005010);
+
+        outl(inl(0xcf005010) | 0x6000, 0xcf005010);
+        outl(0x01, 0xcf005008);
+        outl(0xa9, 0xcf00500c);
+        outl(0xe000, 0xcf005010);
 
         /* Clock frequency = (24/4)*postmult */
         outl(4, 0xcf005018);
         outl(postmult, 0xcf00501c);
 
-        outl(0xe000, 0xcf005010);
-
         /* Wait for PLL relock? */
-        udelay(2000);
+        udelay(200);
 
-        /* Select PLL as clock source? */
-        outl(0xa8, 0xcf00500c);
+        outl(0x02, 0xcf005008);
     }
 }
 #elif !defined(BOOTLOADER)
 static void ipod_set_cpu_speed(void)
 {
+    outl(0xd19b, 0xcf005038);
+
     outl(0x02, 0xcf005008);
     outl(0x55, 0xcf00500c);
     outl(0x6000, 0xcf005010);
-#if 1
-    // 75  MHz (24/24 * 75) (default)
-    outl(24, 0xcf005018);
-    outl(75, 0xcf00501c);
-#endif
 
-#if 0
-    // 66 MHz (24/3 * 8)
-    outl(3, 0xcf005018);
-    outl(8, 0xcf00501c);
-#endif
+    /* 78  MHz (24*13/4) */
+    outl(4, 0xcf005018);
+    outl(13, 0xcf00501c);
 
     outl(0xe000, 0xcf005010);
 
@@ -148,9 +142,15 @@ void system_init(void)
         MMAP3_LOGICAL  = 0x20000000 | 0x3a00;
         MMAP3_PHYSICAL = 0x00000000 | 0x3f84;
 
-        outl(-1, 0xcf00101c);
-        outl(-1, 0xcf001028);
-        outl(-1, 0xcf001038);
+        INT_FORCED_CLR = -1;
+        CPU_INT_CLR    = -1;
+        COP_INT_CLR    = -1;
+
+        GPIOA_INT_EN   = 0;
+        GPIOB_INT_EN   = 0;
+        GPIOC_INT_EN   = 0;
+        GPIOD_INT_EN   = 0;
+
 #ifndef HAVE_ADJUSTABLE_CPU_FREQ
         ipod_set_cpu_speed();
 #endif