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authorMichael Sevakis <jethead71@rockbox.org>2008-05-07 06:13:35 +0000
committerMichael Sevakis <jethead71@rockbox.org>2008-05-07 06:13:35 +0000
commit607b63a8278bfce55ca32356c5df17e2a029eda0 (patch)
treee831207831ae9ce98409fbc808e0df24151a5863
parentbc1ce741c95faa7f918bb39de7cfe9eed9b34f57 (diff)
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Gigabeat S technical correction: Fix instruction order because clean dcache operand is SBZ.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17401 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r--firmware/target/arm/imx31/crt0.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/firmware/target/arm/imx31/crt0.S b/firmware/target/arm/imx31/crt0.S
index bc63a7d..046578b 100644
--- a/firmware/target/arm/imx31/crt0.S
+++ b/firmware/target/arm/imx31/crt0.S
@@ -76,8 +76,8 @@ remap_start:
mrc p15, 0, r3, c1, c0, 0 /* perform writeback if D cache is enabled */
tst r3, #(1 << 2) /* dcache? */
tsteq r3, #(1 << 12) /* or icache? */
- mcrne p15, 0, r0, c7, c10, 0 /* clean dcache */
mov r0, #0
+ mcrne p15, 0, r0, c7, c10, 0 /* clean dcache */
mcrne p15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */
mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffer */