gigabeatS: Fix the timer startup oddness. Seems it likes the interrupt clear at the module level after enabling the vector.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16226 a1c6a512-1295-4272-9138-f99709370657

2 files changed, 3 insertions, 8 deletions

diff --git a/firmware/target/arm/imx31/gigabeat-s/ata-imx31.c b/firmware/target/arm/imx31/gigabeat-s/ata-imx31.c
index a61e848..d4d5f66 100644
--- a/firmware/target/arm/imx31/gigabeat-s/ata-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/ata-imx31.c
@@ -44,7 +44,7 @@ void ata_enable(bool on)
 
 bool ata_is_coldstart(void)
 {
-    return 0;
+    return true;
 }
 
 unsigned long get_pll(bool serial) {
diff --git a/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c b/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c
index 7f88240..3c44a15 100644
--- a/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c
@@ -41,7 +41,6 @@ void tick_start(unsigned int interval_in_ms)
      * Count from load value */
     EPITCR1 = (0x3 << 24) | (1 << 19) | (32 << 4) |
               (1 << 3) | (1 << 2) | (1 << 1);
-    EPITSR1 = 1;                /* Clear any pending interrupt */
 #ifndef BOOTLOADER
     EPITLR1 = interval_in_ms;
     EPITCMPR1 = 0;              /* Event when counter reaches 0 */
@@ -49,12 +48,8 @@ void tick_start(unsigned int interval_in_ms)
 #else
     (void)interval_in_ms;
 #endif
+    EPITSR1 = 1;                /* Clear any pending interrupt after
+                                   enabling the vector */
 
     EPITCR1 |= (1 << 0);        /* Enable the counter */
-
-    /* Why does only this trigger the counter? Remove when we find out. */
-    asm volatile (
-        "mcr p15, 0, %0, c7, c0, 4 \n"
-        : : "r" (0)
-    );
 }