diff options
| author | Marcoen Hirschberg <marcoen@gmail.com> | 2008-06-27 23:24:34 +0000 |
|---|---|---|
| committer | Marcoen Hirschberg <marcoen@gmail.com> | 2008-06-27 23:24:34 +0000 |
| commit | 7b10ef9a7c55764d1b6815fd0871cb51ff0205f9 (patch) | |
| tree | 0b2056ef0334e45107b02118040baae49d51b142 | |
| parent | 5c763f4001c1634ea62ded26339df52494e6c718 (diff) | |
| download | rockbox-7b10ef9a7c55764d1b6815fd0871cb51ff0205f9.zip rockbox-7b10ef9a7c55764d1b6815fd0871cb51ff0205f9.tar.gz rockbox-7b10ef9a7c55764d1b6815fd0871cb51ff0205f9.tar.bz2 rockbox-7b10ef9a7c55764d1b6815fd0871cb51ff0205f9.tar.xz | |
initial Meizu M6SL port (take 2)
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17819 a1c6a512-1295-4272-9138-f99709370657
26 files changed, 2092 insertions, 9 deletions
diff --git a/apps/SOURCES b/apps/SOURCES index 01d3121..e70e32b 100644 --- a/apps/SOURCES +++ b/apps/SOURCES @@ -187,6 +187,8 @@ keymaps/keymap-mr500.c keymaps/keymap-mr100.c #elif CONFIG_KEYPAD == COWOND2_PAD keymaps/keymap-cowond2.c +#elif CONFIG_KEYPAD == MEIZU_M6SL_PAD +keymaps/keymap-meizu-m6sl.c #elif CONFIG_KEYPAD == CREATIVEZVM_PAD keymaps/keymap-creativezvm.c #elif CONFIG_KEYPAD == CREATIVEZV_PAD diff --git a/apps/keymaps/keymap-meizu-m6sl.c b/apps/keymaps/keymap-meizu-m6sl.c new file mode 100644 index 0000000..a473c88 --- /dev/null +++ b/apps/keymaps/keymap-meizu-m6sl.c @@ -0,0 +1,303 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id$ + * + * Copyright (C) 2006 Jonathan Gordon + * + * All files in this archive are subject to the GNU General Public License. + * See the file COPYING in the source tree root for full license agreement. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ + +/* Button Code Definitions for the toshiba gigabeat target */ +#include <stdio.h> +#include <string.h> +#include <stdlib.h> + +#include "config.h" +#include "action.h" +#include "button.h" +#include "settings.h" + +/* + * The format of the list is as follows + * { Action Code, Button code, Prereq button code } + * if there's no need to check the previous button's value, use BUTTON_NONE + * Insert LAST_ITEM_IN_LIST at the end of each mapping + */ + +/* CONTEXT_CUSTOM's used in this file... + +CONTEXT_CUSTOM|CONTEXT_TREE = the standard list/tree defines (without directions) +CONTEXT_CUSTOM|CONTEXT_SETTINGS = the direction keys for the eq/col picker screens + i.e where up/down is inc/dec + CONTEXT_SETTINGS = up/down is prev/next, l/r is inc/dec + +*/ + + +static const struct button_mapping button_context_standard[] = { + { ACTION_STD_PREV, BUTTON_UP, BUTTON_NONE }, + { ACTION_STD_PREVREPEAT, BUTTON_UP|BUTTON_REPEAT, BUTTON_NONE }, + { ACTION_STD_NEXT, BUTTON_DOWN, BUTTON_NONE }, + { ACTION_STD_NEXTREPEAT, BUTTON_DOWN|BUTTON_REPEAT, BUTTON_NONE }, + + { ACTION_STD_CANCEL, BUTTON_LEFT, BUTTON_NONE }, + + { ACTION_STD_CONTEXT, BUTTON_SELECT|BUTTON_REPEAT,BUTTON_SELECT }, + + { ACTION_STD_QUICKSCREEN, BUTTON_MENU|BUTTON_REPEAT, BUTTON_MENU }, + { ACTION_STD_MENU, BUTTON_MENU|BUTTON_REL, BUTTON_MENU }, + + { ACTION_STD_OK, BUTTON_SELECT|BUTTON_REL, BUTTON_SELECT }, + { ACTION_STD_OK, BUTTON_RIGHT, BUTTON_NONE }, + + LAST_ITEM_IN_LIST +}; /* button_context_standard */ + + +static const struct button_mapping button_context_wps[] = { + { ACTION_WPS_PLAY, BUTTON_PLAY|BUTTON_REL, BUTTON_PLAY }, + { ACTION_WPS_STOP, BUTTON_PLAY|BUTTON_REPEAT, BUTTON_NONE }, + + { ACTION_WPS_SKIPNEXT, BUTTON_RIGHT|BUTTON_REL, BUTTON_RIGHT }, + { ACTION_WPS_SKIPPREV, BUTTON_LEFT|BUTTON_REL, BUTTON_LEFT }, + + { ACTION_WPS_SEEKBACK, BUTTON_LEFT|BUTTON_REPEAT, BUTTON_NONE }, + { ACTION_WPS_SEEKFWD, BUTTON_RIGHT|BUTTON_REPEAT, BUTTON_NONE }, + { ACTION_WPS_STOPSEEK, BUTTON_LEFT|BUTTON_REL, BUTTON_LEFT|BUTTON_REPEAT }, + { ACTION_WPS_STOPSEEK, BUTTON_RIGHT|BUTTON_REL, BUTTON_RIGHT|BUTTON_REPEAT }, + + { ACTION_WPS_ABSETB_NEXTDIR, BUTTON_PLAY|BUTTON_RIGHT, BUTTON_NONE }, + { ACTION_WPS_ABSETA_PREVDIR, BUTTON_PLAY|BUTTON_LEFT, BUTTON_NONE }, + { ACTION_WPS_ABRESET, BUTTON_PLAY|BUTTON_SELECT, BUTTON_NONE }, + + { ACTION_WPS_VOLDOWN, BUTTON_DOWN|BUTTON_REPEAT, BUTTON_NONE }, + { ACTION_WPS_VOLDOWN, BUTTON_DOWN, BUTTON_NONE }, + { ACTION_WPS_VOLUP, BUTTON_UP|BUTTON_REPEAT, BUTTON_NONE }, + { ACTION_WPS_VOLUP, BUTTON_UP, BUTTON_NONE }, + + { ACTION_WPS_PITCHSCREEN, BUTTON_PLAY|BUTTON_UP, BUTTON_PLAY }, + { ACTION_WPS_PITCHSCREEN, BUTTON_PLAY|BUTTON_DOWN, BUTTON_PLAY }, + + { ACTION_WPS_QUICKSCREEN, BUTTON_MENU|BUTTON_REPEAT, BUTTON_MENU }, + { ACTION_WPS_MENU, BUTTON_MENU|BUTTON_REL, BUTTON_MENU }, + { ACTION_WPS_CONTEXT, BUTTON_SELECT|BUTTON_REPEAT, BUTTON_SELECT }, + + { ACTION_WPS_ID3SCREEN, BUTTON_PLAY|BUTTON_MENU, BUTTON_NONE }, + { ACTION_WPS_BROWSE, BUTTON_SELECT|BUTTON_REL, BUTTON_SELECT }, + + LAST_ITEM_IN_LIST +}; /* button_context_wps */ + +static const struct button_mapping button_context_list[] = { + { ACTION_LISTTREE_PGUP, BUTTON_PLAY|BUTTON_UP, BUTTON_PLAY }, + { ACTION_LISTTREE_PGUP, BUTTON_UP|BUTTON_REL, BUTTON_PLAY|BUTTON_UP }, + { ACTION_LISTTREE_PGUP, BUTTON_PLAY|BUTTON_UP|BUTTON_REPEAT, BUTTON_NONE }, + { ACTION_LISTTREE_PGDOWN, BUTTON_PLAY|BUTTON_DOWN, BUTTON_PLAY }, + { ACTION_LISTTREE_PGDOWN, BUTTON_DOWN|BUTTON_REL, BUTTON_PLAY|BUTTON_DOWN }, + { ACTION_LISTTREE_PGDOWN, BUTTON_PLAY|BUTTON_DOWN|BUTTON_REPEAT, BUTTON_NONE }, + + LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_STD) +}; /* button_context_list */ + +static const struct button_mapping button_context_tree[] = { + { ACTION_TREE_WPS, BUTTON_PLAY|BUTTON_REL, BUTTON_PLAY }, + { ACTION_TREE_STOP, BUTTON_PLAY|BUTTON_REPEAT, BUTTON_NONE }, + + LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_LIST) +}; /* button_context_tree */ + +static const struct button_mapping button_context_listtree_scroll_with_combo[] = { + { ACTION_NONE, BUTTON_PLAY, BUTTON_NONE }, + { ACTION_TREE_PGLEFT, BUTTON_PLAY|BUTTON_LEFT, BUTTON_PLAY }, + { ACTION_TREE_PGLEFT, BUTTON_LEFT|BUTTON_REL, BUTTON_PLAY|BUTTON_LEFT }, + { ACTION_TREE_PGLEFT, BUTTON_PLAY|BUTTON_LEFT, BUTTON_LEFT|BUTTON_REL }, + { ACTION_TREE_ROOT_INIT, BUTTON_PLAY|BUTTON_LEFT|BUTTON_REPEAT, BUTTON_PLAY|BUTTON_LEFT }, + { ACTION_TREE_PGLEFT, BUTTON_PLAY|BUTTON_LEFT|BUTTON_REPEAT, BUTTON_NONE }, + { ACTION_TREE_PGRIGHT, BUTTON_PLAY|BUTTON_RIGHT, BUTTON_PLAY }, + { ACTION_TREE_PGRIGHT, BUTTON_RIGHT|BUTTON_REL, BUTTON_PLAY|BUTTON_RIGHT }, + { ACTION_TREE_PGRIGHT, BUTTON_PLAY|BUTTON_RIGHT, BUTTON_RIGHT|BUTTON_REL }, + { ACTION_TREE_PGRIGHT, BUTTON_PLAY|BUTTON_RIGHT|BUTTON_REPEAT, BUTTON_NONE }, + LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_CUSTOM|CONTEXT_TREE), +}; + +static const struct button_mapping button_context_listtree_scroll_without_combo[] = { + { ACTION_NONE, BUTTON_LEFT, BUTTON_NONE }, + { ACTION_STD_CANCEL, BUTTON_LEFT|BUTTON_REL, BUTTON_LEFT }, + { ACTION_TREE_ROOT_INIT, BUTTON_LEFT|BUTTON_REPEAT, BUTTON_LEFT }, + { ACTION_TREE_PGLEFT, BUTTON_LEFT|BUTTON_REPEAT, BUTTON_NONE }, + { ACTION_TREE_PGLEFT, BUTTON_LEFT|BUTTON_REL, BUTTON_LEFT|BUTTON_REPEAT }, + { ACTION_NONE, BUTTON_RIGHT, BUTTON_NONE }, + { ACTION_STD_OK, BUTTON_RIGHT|BUTTON_REL, BUTTON_RIGHT }, + { ACTION_TREE_PGRIGHT, BUTTON_RIGHT|BUTTON_REPEAT, BUTTON_NONE }, + { ACTION_TREE_PGRIGHT, BUTTON_RIGHT|BUTTON_REL, BUTTON_RIGHT|BUTTON_REPEAT }, + LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_CUSTOM|CONTEXT_TREE), +}; + +static const struct button_mapping button_context_settings[] = { + { ACTION_SETTINGS_INC, BUTTON_UP, BUTTON_NONE }, + { ACTION_SETTINGS_INCREPEAT, BUTTON_UP|BUTTON_REPEAT, BUTTON_NONE }, + { ACTION_SETTINGS_DEC, BUTTON_DOWN, BUTTON_NONE }, + { ACTION_SETTINGS_DECREPEAT, BUTTON_DOWN|BUTTON_REPEAT, BUTTON_NONE }, + { ACTION_STD_PREV, BUTTON_LEFT, BUTTON_NONE }, + { ACTION_STD_PREVREPEAT, BUTTON_LEFT|BUTTON_REPEAT, BUTTON_NONE }, + { ACTION_STD_NEXT, BUTTON_RIGHT, BUTTON_NONE }, + { ACTION_STD_NEXTREPEAT, BUTTON_RIGHT|BUTTON_REPEAT, BUTTON_NONE }, + { ACTION_SETTINGS_RESET, BUTTON_PLAY, BUTTON_NONE }, + + LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_STD) +}; /* button_context_settings */ + +static const struct button_mapping button_context_settings_right_is_inc[] = { + { ACTION_SETTINGS_INC, BUTTON_RIGHT, BUTTON_NONE }, + { ACTION_SETTINGS_INCREPEAT, BUTTON_RIGHT|BUTTON_REPEAT, BUTTON_NONE }, + { ACTION_SETTINGS_DEC, BUTTON_LEFT, BUTTON_NONE }, + { ACTION_SETTINGS_DECREPEAT, BUTTON_LEFT|BUTTON_REPEAT, BUTTON_NONE }, + { ACTION_STD_PREV, BUTTON_UP, BUTTON_NONE }, + { ACTION_STD_PREVREPEAT, BUTTON_UP|BUTTON_REPEAT, BUTTON_NONE }, + { ACTION_STD_NEXT, BUTTON_DOWN, BUTTON_NONE }, + { ACTION_STD_NEXTREPEAT, BUTTON_DOWN|BUTTON_REPEAT, BUTTON_NONE }, + { ACTION_SETTINGS_RESET, BUTTON_PLAY, BUTTON_NONE }, + + LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_STD) +}; /* button_context_settingsgraphical */ + +static const struct button_mapping button_context_yesno[] = { + { ACTION_YESNO_ACCEPT, BUTTON_SELECT, BUTTON_NONE }, + LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_STD) +}; /* button_context_settings_yesno */ + +static const struct button_mapping button_context_colorchooser[] = { + { ACTION_STD_OK, BUTTON_PLAY|BUTTON_REL, BUTTON_NONE }, + LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_CUSTOM|CONTEXT_SETTINGS), +}; /* button_context_colorchooser */ + +static const struct button_mapping button_context_eq[] = { + { ACTION_STD_OK, BUTTON_SELECT|BUTTON_REL, BUTTON_NONE }, + LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_CUSTOM|CONTEXT_SETTINGS), +}; /* button_context_eq */ + +/** Bookmark Screen **/ +static const struct button_mapping button_context_bmark[] = { + { ACTION_BMS_DELETE, BUTTON_PLAY, BUTTON_NONE }, + + LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_LIST), +}; /* button_context_bmark */ + +static const struct button_mapping button_context_time[] = { + { ACTION_STD_CANCEL, BUTTON_LEFT, BUTTON_NONE }, + { ACTION_STD_OK, BUTTON_PLAY, BUTTON_NONE }, + LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_SETTINGS), +}; /* button_context_time */ + +static const struct button_mapping button_context_quickscreen[] = { + { ACTION_QS_DOWNINV, BUTTON_UP, BUTTON_NONE }, + { ACTION_QS_DOWNINV, BUTTON_UP|BUTTON_REPEAT, BUTTON_NONE }, + { ACTION_QS_DOWN, BUTTON_DOWN, BUTTON_NONE }, + { ACTION_QS_DOWN, BUTTON_DOWN|BUTTON_REPEAT, BUTTON_NONE }, + { ACTION_QS_LEFT, BUTTON_LEFT, BUTTON_NONE }, + { ACTION_QS_LEFT, BUTTON_LEFT|BUTTON_REPEAT, BUTTON_NONE }, + { ACTION_QS_RIGHT, BUTTON_RIGHT, BUTTON_NONE }, + { ACTION_QS_RIGHT, BUTTON_RIGHT|BUTTON_REPEAT, BUTTON_NONE }, + { ACTION_STD_CANCEL, BUTTON_MENU, BUTTON_NONE }, + + LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_STD) +}; /* button_context_quickscreen */ + +static const struct button_mapping button_context_pitchscreen[] = { + { ACTION_PS_INC_SMALL, BUTTON_UP, BUTTON_NONE }, + { ACTION_PS_INC_BIG, BUTTON_UP|BUTTON_REPEAT, BUTTON_NONE }, + { ACTION_PS_DEC_SMALL, BUTTON_DOWN, BUTTON_NONE }, + { ACTION_PS_DEC_BIG, BUTTON_DOWN|BUTTON_REPEAT, BUTTON_NONE }, + { ACTION_PS_NUDGE_LEFT, BUTTON_LEFT, BUTTON_NONE }, + { ACTION_PS_NUDGE_LEFTOFF, BUTTON_LEFT|BUTTON_REL, BUTTON_NONE }, + { ACTION_PS_NUDGE_RIGHT, BUTTON_RIGHT, BUTTON_NONE }, + { ACTION_PS_NUDGE_RIGHTOFF, BUTTON_RIGHT|BUTTON_REL, BUTTON_NONE }, + { ACTION_PS_TOGGLE_MODE, BUTTON_MENU, BUTTON_NONE }, + { ACTION_PS_RESET, BUTTON_PLAY, BUTTON_NONE }, + { ACTION_PS_EXIT, BUTTON_PLAY|BUTTON_REPEAT, BUTTON_NONE }, + + LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_STD) +}; /* button_context_pitchcreen */ + +static const struct button_mapping button_context_keyboard[] = { + { ACTION_KBD_LEFT, BUTTON_LEFT, BUTTON_NONE }, + { ACTION_KBD_LEFT, BUTTON_LEFT|BUTTON_REPEAT, BUTTON_NONE }, + { ACTION_KBD_RIGHT, BUTTON_RIGHT, BUTTON_NONE }, + { ACTION_KBD_RIGHT, BUTTON_RIGHT|BUTTON_REPEAT, BUTTON_NONE }, + { ACTION_KBD_CURSOR_LEFT, BUTTON_PLAY|BUTTON_LEFT, BUTTON_NONE }, + { ACTION_KBD_CURSOR_LEFT, BUTTON_PLAY|BUTTON_LEFT|BUTTON_REPEAT, BUTTON_NONE }, + { ACTION_KBD_CURSOR_RIGHT, BUTTON_PLAY|BUTTON_RIGHT, BUTTON_NONE }, + { ACTION_KBD_CURSOR_RIGHT, BUTTON_PLAY|BUTTON_RIGHT|BUTTON_REPEAT, BUTTON_NONE }, + { ACTION_KBD_SELECT, BUTTON_SELECT, BUTTON_NONE }, + { ACTION_KBD_PAGE_FLIP, BUTTON_PLAY|BUTTON_MENU, BUTTON_NONE }, + { ACTION_KBD_DONE, BUTTON_PLAY|BUTTON_REL, BUTTON_PLAY }, + { ACTION_KBD_ABORT, BUTTON_PLAY|BUTTON_REPEAT, BUTTON_NONE }, + { ACTION_KBD_BACKSPACE, BUTTON_MENU, BUTTON_NONE }, + { ACTION_KBD_BACKSPACE, BUTTON_MENU|BUTTON_REPEAT, BUTTON_NONE }, + { ACTION_KBD_UP, BUTTON_UP, BUTTON_NONE }, + { ACTION_KBD_UP, BUTTON_UP|BUTTON_REPEAT, BUTTON_NONE }, + { ACTION_KBD_DOWN, BUTTON_DOWN, BUTTON_NONE }, + { ACTION_KBD_DOWN, BUTTON_DOWN|BUTTON_REPEAT, BUTTON_NONE }, +// { ACTION_KBD_MORSE_INPUT, BUTTON_PLAY|BUTTON_POWER, BUTTON_NONE }, + { ACTION_KBD_MORSE_SELECT, BUTTON_SELECT|BUTTON_REL, BUTTON_NONE }, + + LAST_ITEM_IN_LIST +}; /* button_context_keyboard */ + + +const struct button_mapping* get_context_mapping(int context) +{ + switch (context) + { + case CONTEXT_STD: + return button_context_standard; + case CONTEXT_WPS: + return button_context_wps; + + case CONTEXT_LIST: + return button_context_list; + case CONTEXT_MAINMENU: + case CONTEXT_TREE: + if (global_settings.hold_lr_for_scroll_in_list) + return button_context_listtree_scroll_without_combo; + else + return button_context_listtree_scroll_with_combo; + case CONTEXT_CUSTOM|CONTEXT_TREE: + return button_context_tree; + + case CONTEXT_SETTINGS: + return button_context_settings; + case CONTEXT_CUSTOM|CONTEXT_SETTINGS: + return button_context_settings_right_is_inc; + + case CONTEXT_SETTINGS_COLOURCHOOSER: + return button_context_colorchooser; + case CONTEXT_SETTINGS_EQ: + return button_context_eq; + + case CONTEXT_SETTINGS_TIME: + return button_context_time; + + case CONTEXT_YESNOSCREEN: + return button_context_yesno; + case CONTEXT_BOOKMARKSCREEN: + return button_context_bmark; + case CONTEXT_QUICKSCREEN: + return button_context_quickscreen; + case CONTEXT_PITCHSCREEN: + return button_context_pitchscreen; + case CONTEXT_KEYBOARD: + return button_context_keyboard; + } + return button_context_standard; +} diff --git a/bootloader/SOURCES b/bootloader/SOURCES index 37011dd..19e40e2 100644 --- a/bootloader/SOURCES +++ b/bootloader/SOURCES @@ -29,4 +29,6 @@ iriver_h300.c mrobe500.c #elif defined(CPU_TCC77X) || defined(CPU_TCC780X) telechips.c +#elif defined(MEIZU_M6SL) +meizu_m6sl.c #endif diff --git a/bootloader/meizu_m6sl.c b/bootloader/meizu_m6sl.c new file mode 100644 index 0000000..3bafd79 --- /dev/null +++ b/bootloader/meizu_m6sl.c @@ -0,0 +1,84 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id$ + * + * Copyright (C) 2006 by Greg White + * + * All files in this archive are subject to the GNU General Public License. + * See the file COPYING in the source tree root for full license agreement. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#include "config.h" + +#include <stdlib.h> +#include <stdio.h> +#include "inttypes.h" +#include "string.h" +#include "cpu.h" +#include "system.h" +#include "lcd.h" +#include "kernel.h" +#include "thread.h" +#include "ata.h" +#include "fat.h" +#include "disk.h" +#include "font.h" +#include "adc.h" +#include "backlight.h" +#include "backlight-target.h" +#include "button.h" +#include "panic.h" +#include "power.h" +#include "file.h" +#include "common.h" +#include "rbunicode.h" +#include "usb.h" + +#include <stdarg.h> + +char version[] = APPSVERSION; + +void main(void) +{ + //Set backlight pin to output and enable + int oldval = PCON0; + PCON0 = ((oldval & ~(3 << 4)) | (1 << 4)); + PDAT0 |= (1 << 2); + + //Set PLAY to input + oldval = PCON1; + PCON1 = ((oldval & ~(0xf << 16)) | (0 << 16)); + + //Set the piezo pins to output + oldval = PCON5; + PCON5 = ((oldval & ~((0xf << 4) | (0xf << 8))) | ((1 << 0) | (1 << 4))); + PDAT5 &= ~((1 << 1) | (1 << 2)); //should not be needed + + PDAT5 |= (1 << 1); //Toggle piezo + + + //toggle backlight on PLAY + while(true) + { + // Wait for play to be pressed + while(!(PDAT1 & (1 << 4))) + { + } + + PDAT5 ^= (1 << 1); //Toggle piezo + + PDAT0 ^= (1 << 2); //Toggle packlight + + // Wait for play to be released + while(PDAT1 & (1 << 4)) + { + } + } +} + diff --git a/firmware/SOURCES b/firmware/SOURCES index 4dca1c1..60adcbe 100644 --- a/firmware/SOURCES +++ b/firmware/SOURCES @@ -355,6 +355,8 @@ target/arm/tcc77x/crt0.S target/arm/tcc780x/crt0.S #elif CONFIG_CPU==IMX31L target/arm/imx31/crt0.S +#elif CONFIG_CPU==S5L8700 +target/arm/s5l8700/crt0.S #elif defined(CPU_ARM) target/arm/crt0.S #endif /* defined(CPU_*) */ @@ -1042,3 +1044,13 @@ target/arm/tcc780x/cowond2/audio-cowond2.c #endif /* BOOTLOADER */ #endif /* SIMULATOR */ #endif /* COWON_D2 */ + +#ifdef MEIZU_M6SL +target/arm/s5l8700/system-s5l8700.c +target/arm/s5l8700/ata-nand-s5l8700.c +target/arm/s5l8700/meizu-m6sl/lcd-m6sl.c +#ifndef SIMULATOR +#ifndef BOOTLOADER +#endif /* BOOTLOADER */ +#endif /* SIMULATOR */ +#endif /* MEIZU_M6SL */ diff --git a/firmware/drivers/tuner/tea5760uk.c b/firmware/drivers/tuner/tea5760uk.c new file mode 100644 index 0000000..8582358 --- /dev/null +++ b/firmware/drivers/tuner/tea5760uk.c @@ -0,0 +1,135 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id$ + * Tuner "middleware" for Philips TEA5760UK chip + * + * Copyright (C) 2004 Jörg Hohensohn + * + * All files in this archive are subject to the GNU General Public License. + * See the file COPYING in the source tree root for full license agreement. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#include "config.h" +#include <stdbool.h> +#include <string.h> +#include <stdlib.h> +#include "kernel.h" +#include "tuner.h" /* tuner abstraction interface */ +#include "fmradio.h" +#include "fmradio_i2c.h" /* physical interface driver */ + +#define I2C_ADR 0xC0 +static unsigned char write_bytes[7] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; + +static void tea5760uk_set_clear(int byte, unsigned char bits, int set) +{ + write_bytes[byte] &= ~bits; + if (set) + write_bytes[byte] |= bits; +} + +/* tuner abstraction layer: set something to the tuner */ +int tea5760uk_set(int setting, int value) +{ + switch(setting) + { + case RADIO_SLEEP: + /* init values */ + write_bytes[0] |= (1<<7); /* mute */ +#if CONFIG_TUNER_XTAL == 32768 + /* 32.768kHz, soft mute, stereo noise cancelling */ + write_bytes[3] |= (1<<4) | (1<<3) | (1<<1); +#else + /* soft mute, stereo noise cancelling */ + write_bytes[3] |= (1<<3) | (1<<1); +#endif + /* sleep / standby mode */ + tea5760uk_set_clear(3, (1<<6), value); + break; + + case RADIO_FREQUENCY: + { + int n; +#if CONFIG_TUNER_XTAL == 32768 + n = (4 * (value - 225000) + 16384) / 32768; +#else + n = (4 * (value - 225000)) / 50000; +#endif + write_bytes[6] = (write_bytes[6] & 0xC0) | (n >> 8); + write_bytes[7] = n; + } + break; + + case RADIO_SCAN_FREQUENCY: + tea5760uk_set(RADIO_FREQUENCY, value); + sleep(HZ/30); + return tea5760uk_get(RADIO_TUNED); + + case RADIO_MUTE: + tea5760uk_set_clear(3, (1<<2), value); + break; + + case RADIO_REGION: + { + const struct tea5760uk_region_data *rd = + &tea5760uk_region_data[value]; + + tea5760uk_set_clear(4, (1<<1), rd->deemphasis); + tea5760uk_set_clear(3, (1<<5), rd->band); + break; + } + case RADIO_FORCE_MONO: + tea5760uk_set_clear(4, (1<<3), value); + break; + default: + return -1; + } + + fmradio_i2c_write(I2C_ADR, write_bytes, sizeof(write_bytes)); + return 1; +} + +/* tuner abstraction layer: read something from the tuner */ +int tea5760uk_get(int setting) +{ + unsigned char read_bytes[16]; + int val = -1; /* default for unsupported query */ + + fmradio_i2c_read(I2C_ADR, read_bytes, sizeof(read_bytes)); + + switch(setting) + { + case RADIO_PRESENT: + val = 1; /* true */ + break; + + case RADIO_TUNED: + val = 0; + if (read_bytes[0] & (1<<4)) /* IF count correct */ + { + val = read_bytes[8] >> 1; /* IF counter */ + val = (abs(val - 0x36) < 2); /* close match */ + } + break; + + case RADIO_STEREO: + val = read_bytes[9] >> 2; + break; + } + + return val; +} + +void tea5760uk_dbg_info(struct tea5760uk_dbg_info *info) +{ + fmradio_i2c_read(I2C_ADR, info->read_regs, 5); + memcpy(info->write_regs, write_bytes, 5); +} diff --git a/firmware/export/config-meizu-m6sl.h b/firmware/export/config-meizu-m6sl.h new file mode 100644 index 0000000..96c163c --- /dev/null +++ b/firmware/export/config-meizu-m6sl.h @@ -0,0 +1,173 @@ +/* + * This config file is for iAudio X5 + */ +#define TARGET_TREE /* this target is using the target tree system */ + +/* For Rolo and boot loader */ +#define MODEL_NUMBER 1 + +/* define this if you have recording possibility */ +//#define HAVE_RECORDING + +/* Define bitmask of input sources - recordable bitmask can be defined + explicitly if different */ +#define INPUT_SRC_CAPS (SRC_CAP_MIC | SRC_CAP_LINEIN | SRC_CAP_FMRADIO) + +/* define the bitmask of hardware sample rates */ +#define HW_SAMPR_CAPS (SAMPR_CAP_88 | SAMPR_CAP_44 | SAMPR_CAP_22 | SAMPR_CAP_11) + +/* define the bitmask of recording sample rates */ +#define REC_SAMPR_CAPS (SAMPR_CAP_88 | SAMPR_CAP_44 | SAMPR_CAP_22 | SAMPR_CAP_11) + +/* define this if you have a bitmap LCD display */ +#define HAVE_LCD_BITMAP + +/* define this if you can flip your LCD */ +//#define HAVE_LCD_FLIP + +/* define this if you have a colour LCD */ +#define HAVE_LCD_COLOR + +/* define this if you want album art for this target */ +#define HAVE_ALBUMART + +/* define this if you can invert the colours on your LCD */ +//#define HAVE_LCD_INVERT + +/* define this if you have access to the quickscreen */ +#define HAVE_QUICKSCREEN + +/* define this if you have access to the pitchscreen */ +#define HAVE_PITCHSCREEN + +/* define this if you would like tagcache to build on this target */ +#define HAVE_TAGCACHE + +/* define this if you have a flash memory storage */ +#define HAVE_FLASH_STORAGE + +/* LCD dimensions */ +#define LCD_WIDTH 320 +#define LCD_HEIGHT 240 +#define LCD_DEPTH 16 /* pseudo 262.144 colors */ +#define LCD_PIXELFORMAT RGB565 /* rgb565 */ + +/* Define this if your LCD can be enabled/disabled */ +//#define HAVE_LCD_ENABLE + +/* Define this if your LCD can be put to sleep. HAVE_LCD_ENABLE + should be defined as well. */ +//#define HAVE_LCD_SLEEP + +#define CONFIG_KEYPAD MEIZU_M6SL_PAD + +//#define AB_REPEAT_ENABLE 1 +//#define ACTION_WPSAB_SINGLE ACTION_WPS_BROWSE + +/* Define this if you do software codec */ +#define CONFIG_CODEC SWCODEC + +/* define this if you have a real-time clock */ +#define CONFIG_RTC RTC_S5L8700 +//#define CONFIG_RTC RTC_S35390A + +#define CONFIG_LCD LCD_MEIZUM6 + +/* Define this if you have the WM8975 audio codec */ +#define HAVE_WM8751 //FIXME + +/* Define this for LCD backlight available */ +#define HAVE_BACKLIGHT +#define HAVE_BACKLIGHT_BRIGHTNESS + +/* Define this if you have a software controlled poweroff */ +#define HAVE_SW_POWEROFF + +/* The number of bytes reserved for loadable codecs */ +#define CODEC_SIZE 0x80000 + +/* The number of bytes reserved for loadable plugins */ +#define PLUGIN_BUFFER_SIZE 0x80000 + +/* FM Tuner */ +#define CONFIG_TUNER TEA5760 +#define CONFIG_TUNER_XTAL 32768 + +//#define HAVE_TLV320 + +/* TLV320 has no tone controls, so we use the software ones */ +#define HAVE_SW_TONE_CONTROLS + +#define BATTERY_CAPACITY_DEFAULT 700 /* default battery capacity */ +#define BATTERY_CAPACITY_MIN 500 /* min. capacity selectable */ +#define BATTERY_CAPACITY_MAX 2250 /* max. capacity selectable */ +#define BATTERY_CAPACITY_INC 50 /* capacity increment */ +#define BATTERY_TYPES_COUNT 1 /* only one type */ + +/* Hardware controlled charging? FIXME */ +#define CONFIG_CHARGING CHARGING_SIMPLE + +#ifndef SIMULATOR + +/* Define this if your LCD can set contrast */ +//#define HAVE_LCD_CONTRAST + +/* Define this if you have a Motorola SCF5250 */ +#define CONFIG_CPU S5L8700 + +/* Define this if you want to use coldfire's i2c interface */ +#define CONFIG_I2C I2C_S5L8700 + +/* define this if the hardware can be powered off while charging */ +#define HAVE_POWEROFF_WHILE_CHARGING + +/* The size of the flash ROM */ +#define FLASH_SIZE 0x400000 + +/* Define this to the CPU frequency */ +#define CPU_FREQ 11289600 + +/* Define this if you have ATA power-off control */ +//#define HAVE_ATA_POWER_OFF + +/* Virtual LED (icon) */ +#define CONFIG_LED LED_VIRTUAL + +/* Offset ( in the firmware file's header ) to the file CRC */ +#define FIRMWARE_OFFSET_FILE_CRC 0 + +/* Offset ( in the firmware file's header ) to the real data */ +#define FIRMWARE_OFFSET_FILE_DATA 8 + +/* USB On-the-go */ +//#define CONFIG_USBOTG USBOTG_M5636 + +/* Define this if you have adjustable CPU frequency */ +#define HAVE_ADJUSTABLE_CPU_FREQ + +#define BOOTFILE_EXT "meizu" +#define BOOTFILE "rockbox." BOOTFILE_EXT +#define BOOTDIR "/.rockbox" + +#define BOOTLOADER_ENTRYPOINT 0x001F0000 +#define FLASH_ENTRYPOINT 0x00001000 +#define FLASH_MAGIC 0xfbfbfbf1 + +#endif /* SIMULATOR */ + +/* Define this for FM radio input available */ +#define HAVE_FMRADIO_IN + +/** Port-specific settings **/ + +/* Main LCD contrast range and defaults */ +#define MIN_CONTRAST_SETTING 1 +#define MAX_CONTRAST_SETTING 30 +#define DEFAULT_CONTRAST_SETTING 19 /* Match boot contrast */ + +/* Main LCD backlight brightness range and defaults */ +/* PCF50506 can output 0%-100% duty cycle but D305A expects %15-100%. */ +#define MIN_BRIGHTNESS_SETTING 1 /* 15/16 (93.75%) */ +#define MAX_BRIGHTNESS_SETTING 13 /* 3/16 (18.75%) */ +#define DEFAULT_BRIGHTNESS_SETTING 8 /* 8/16 (50.00%) = x5 boot default */ + diff --git a/firmware/export/config.h b/firmware/export/config.h index 1a6e5d6..79d50bf 100644 --- a/firmware/export/config.h +++ b/firmware/export/config.h @@ -31,6 +31,8 @@ #define TEA5767 0x02 /* Philips */ #define LV24020LP 0x04 /* Sanyo */ #define SI4700 0x08 /* Silicon Labs */ +#define TEA5760 0x10 /* Philips */ +#define LV240000 0x20 /* Sanyo */ /* CONFIG_CODEC */ #define MAS3587F 3587 @@ -55,6 +57,7 @@ #define TCC771L 771 #define TCC773L 773 #define TCC7801 7801 +#define S5L8700 8700 /* CONFIG_KEYPAD */ #define PLAYER_PAD 1 @@ -86,6 +89,7 @@ #define PHILIPS_SA9200_PAD 27 #define SANSA_C100_PAD 28 #define PHILIPS_HDD1630_PAD 29 +#define MEIZU_M6SL_PAD 30 /* CONFIG_REMOTE_KEYPAD */ #define H100_REMOTE 1 @@ -127,6 +131,7 @@ #define LCD_SA9200 25 /* as used by the Philips SA9200 */ #define LCD_S6B33B2 26 /* as used by the Sansa c100 */ #define LCD_HDD1630 27 /* as used by the Philips HDD1630 */ +#define LCD_MEIZUM6 28 /* as used by the Meizu M6SP and M6SL (various models) */ /* LCD_PIXELFORMAT */ #define HORIZONTAL_PACKING 1 @@ -154,6 +159,7 @@ #define I2C_TCC77X 10 #define I2C_TCC780X 11 #define I2C_DM320 12 /* DM320 style */ +#define I2C_S5L8700 12 /* CONFIG_LED */ #define LED_REAL 1 /* SW controlled LED (Archos recorders, player) */ @@ -177,6 +183,8 @@ #define RTC_TCC780X 11 #define RTC_MR100 12 #define RTC_MC13783 13 /* Freescale MC13783 PMIC */ +#define RTC_S5L8700 14 +#define RTC_S35390A 15 /* USB On-the-go */ #define USBOTG_ISP1362 1362 /* iriver H300 */ @@ -271,6 +279,8 @@ #include "config-hdd1630.h" #elif defined(SANSA_C100) #include "config-c100.h" +#elif defined(MEIZU_M6SL) +#include "config-meizu-m6sl.h" #else /* no known platform */ #endif @@ -426,7 +436,7 @@ #endif #if defined(CPU_PP) || (CONFIG_CPU == PNX0101) || (CONFIG_CPU == S3C2440) \ - || (CONFIG_CPU == DSC25) + || (CONFIG_CPU == DSC25) || (CONFIG_CPU == S5L8700) #define CPU_ARM #define ARM_ARCH 4 /* ARMv4 */ #endif @@ -454,7 +464,8 @@ defined(CPU_COLDFIRE) || /* Coldfire: core, plugins, codecs */ \ defined(CPU_PP) || /* PortalPlayer: core, plugins, codecs */ \ defined(CPU_TCC77X) || /* Telechips: core, plugins, codecs */ \ - (CONFIG_CPU == PNX0101)) + (CONFIG_CPU == PNX0101) || \ + (CONFIG_CPU == S5L8700)) /* Samsing S5L8700: core, plugins, codecs */ #define ICODE_ATTR __attribute__ ((section(".icode"))) #define ICONST_ATTR __attribute__ ((section(".irodata"))) #define IDATA_ATTR __attribute__ ((section(".idata"))) diff --git a/firmware/export/cpu.h b/firmware/export/cpu.h index 08a91a6..ec08812 100644 --- a/firmware/export/cpu.h +++ b/firmware/export/cpu.h @@ -54,3 +54,6 @@ #ifdef CPU_TCC780X #include "tcc780x.h" #endif +#if CONFIG_CPU == S5L8700 +#include "s5l8700.h" +#endif diff --git a/firmware/export/s5l8700.h b/firmware/export/s5l8700.h new file mode 100644 index 0000000..211564e --- /dev/null +++ b/firmware/export/s5l8700.h @@ -0,0 +1,567 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id: S5L8700X.h 2008-03-27 Marcoen Hirschberg, Bart van Adrichem $ + * + * Copyright (C) 2008 by Marcoen Hirschberg, Bart van Adrichem + * + * All files in this archive are subject to the GNU General Public License. + * See the file COPYING in the source tree root for full license agreement. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ + +#define REG8_PTR_T volatile uint8_t * +#define REG16_PTR_T volatile uint16_t * +#define REG32_PTR_T volatile uint32_t * + +/* 04. CALMADM2E */ + +/* Following registers are mapped on IO Area in data memory area of Calm. */ +#define CONFIG0 (*(REG16_PTR_T)(0x3F000000)) /* configuration/control register 0 */ +#define CONFIG1 (*(REG16_PTR_T)(0x3F000002)) /* configuration/control register 1*/ +#define COMMUN (*(REG16_PTR_T)(0x3F000004)) /* Communication Control Register */ +#define DDATA0 (*(REG16_PTR_T)(0x3F000006)) /* Communication data from host to ADM */ +#define DDATA1 (*(REG16_PTR_T)(0x3F000008)) /* Communication data from host to ADM */ +#define DDATA2 (*(REG16_PTR_T)(0x3F00000A)) /* Communication data from host to ADM */ +#define DDATA3 (*(REG16_PTR_T)(0x3F00000C)) /* Communication data from host to ADM */ +#define DDATA4 (*(REG16_PTR_T)(0x3F00000E)) /* Communication data from host to ADM */ +#define DDATA5 (*(REG16_PTR_T)(0x3F000010)) /* Communication data from host to ADM */ +#define DDATA6 (*(REG16_PTR_T)(0x3F000012)) /* Communication data from host to ADM */ +#define DDATA7 (*(REG16_PTR_T)(0x3F000014)) /* Communication data from host to ADM */ +#define UDATA0 (*(REG16_PTR_T)(0x3F000016)) /* Communication data from ADM to host */ +#define UDATA1 (*(REG16_PTR_T)(0x3F000018)) /* Communication data from ADM to host */ +#define UDATA2 (*(REG16_PTR_T)(0x3F00001A)) /* Communication data from ADM to host */ +#define UDATA3 (*(REG16_PTR_T)(0x3F00001C)) /* Communication data from ADM to host */ +#define UDATA4 (*(REG16_PTR_T)(0x3F00001E)) /* Communication data from ADM to host */ +#define UDATA5 (*(REG16_PTR_T)(0x3F000020)) /* Communication data from ADM to host */ +#define UDATA6 (*(REG16_PTR_T)(0x3F000022)) /* Communication data from ADM to host */ +#define UDATA7 (*(REG16_PTR_T)(0x3F000024)) /* Communication data from ADM to host */ +#define IBASE_H (*(REG16_PTR_T)(0x3F000026)) /* Higher half of start address for ADM instruction area */ +#define IBASE_L (*(REG16_PTR_T)(0x3F000028)) /* Lower half of start address for ADM instruction area */ +#define DBASE_H (*(REG16_PTR_T)(0x3F00002A)) /* Higher half of start address for CalmRISC data area */ +#define DBASE_L (*(REG16_PTR_T)(0x3F00002C)) /* Lower half of start address for CalmRISC data area */ +#define XBASE_H (*(REG16_PTR_T)(0x3F00002E)) /* Higher half of start address for Mac X area */ +#define XBASE_L (*(REG16_PTR_T)(0x3F000030)) /* Lower half of start address for Mac X area */ +#define YBASE_H (*(REG16_PTR_T)(0x3F000032)) /* Higher half of start address for Mac Y area */ +#define YBASE_L (*(REG16_PTR_T)(0x3F000034)) /* Lower half of start address for Mac Y area */ +#define S0BASE_H (*(REG16_PTR_T)(0x3F000036)) /* Higher half of start address for sequential buffer 0 area */ +#define S0BASE_L (*(REG16_PTR_T)(0x3F000038)) /* Lower half of start address for sequential buffer 0 area */ +#define S1BASE_H (*(REG16_PTR_T)(0x3F00003A)) /* Higher half of start address for sequential buffer 1 area */ +#define S1BASE_L (*(REG16_PTR_T)(0x3F00003C)) /* Lower half of start address for sequential buffer 1 area */ +#define CACHECON (*(REG16_PTR_T)(0x3F00003E)) /* Cache Control Register */ +#define CACHESTAT (*(REG16_PTR_T)(0x3F000040)) /* Cache status register */ +#define SBFCON (*(REG16_PTR_T)(0x3F000042)) /* Sequential Buffer Control Register */ +#define SBFSTAT (*(REG16_PTR_T)(0x3F000044)) /* Sequential Buffer Status Register */ +#define SBL0OFF_H (*(REG16_PTR_T)(0x3F000046)) /* Higher bits of Offset register of sequential block 0 area */ +#define SBL0OFF_L (*(REG16_PTR_T)(0x3F000048)) /* Lower bits of Offset register of sequential block 0 area */ +#define SBL1OFF_H (*(REG16_PTR_T)(0x3F00004A)) /* Higher bits of Offset register of sequential block 1 area */ +#define SBL1OFF_L (*(REG16_PTR_T)(0x3F00004C)) /* Lower bits of Offset register of sequential block 1 area */ +#define SBL0BEGIN_H (*(REG16_PTR_T)(0x3F00004E)) /* Higher bits of Begin Offset of sequential block 0 area in ring mode */ +#define SBL0BEGIN_L (*(REG16_PTR_T)(0x3F000050)) /* Lower bits of Begin Offset of sequential block 0 area in ring mode */ +#define SBL1BEGIN_H (*(REG16_PTR_T)(0x3F000052)) /* Higher bits of Begin Offset of sequential block 1 area in ring mode */ +#define SBL1BEGIN_L (*(REG16_PTR_T)(0x3F000054)) /* Lower bits of Begin Offset of sequential block 1 area in ring mode */ +#define SBL0END_H (*(REG16_PTR_T)(0x3F000056)) /* Lower bits of End Offset of sequential block 0 area in ring mode */ +#define SBL0END_L (*(REG16_PTR_T)(0x3F000058)) /* Higher bits of End Offset of sequential block 0 area in ring mode */ +#define SBL1END_H (*(REG16_PTR_T)(0x3F00005A)) /* Lower bits of End Offset of sequential block 1 area in ring mode */ +#define SBL1END_L (*(REG16_PTR_T)(0x3F00005C)) /* Higher bits of End Offset of sequential block 1 area in ring mode */ + +/* Following registers are components of SFRS of the target system */ +#define ADM_CONFIG (*(REG32_PTR_T)(0x39000000)) /* Configuration/Control Register */ +#define ADM_COMMUN (*(REG32_PTR_T)(0x39000004)) /* Communication Control Register */ +#define ADM_DDATA0 (*(REG32_PTR_T)(0x39000010)) /* Communication data from host to ADM */ +#define ADM_DDATA1 (*(REG32_PTR_T)(0x39000014)) /* Communication data from host to ADM */ +#define ADM_DDATA2 (*(REG32_PTR_T)(0x39000018)) /* Communication data from host to ADM */ +#define ADM_DDATA3 (*(REG32_PTR_T)(0x3900001C)) /* Communication data from host to ADM */ +#define ADM_DDATA4 (*(REG32_PTR_T)(0x39000020)) /* Communication data from host to ADM */ +#define ADM_DDATA5 (*(REG32_PTR_T)(0x39000024)) /* Communication data from host to ADM */ +#define ADM_DDATA6 (*(REG32_PTR_T)(0x39000028)) /* Communication data from host to ADM */ +#define ADM_DDATA7 (*(REG32_PTR_T)(0x3900002C)) /* Communication data from host to ADM */ +#define ADM_UDATA0 (*(REG32_PTR_T)(0x39000030)) /* Communication data from ADM to host */ +#define ADM_UDATA1 (*(REG32_PTR_T)(0x39000034)) /* Communication data from ADM to host */ +#define ADM_UDATA2 (*(REG32_PTR_T)(0x39000038)) /* Communication data from ADM to host */ +#define ADM_UDATA3 (*(REG32_PTR_T)(0x3900003C)) /* Communication data from ADM to host */ +#define ADM_UDATA4 (*(REG32_PTR_T)(0x39000040)) /* Communication data from ADM to host */ +#define ADM_UDATA5 (*(REG32_PTR_T)(0x39000044)) /* Communication data from ADM to host */ +#define ADM_UDATA6 (*(REG32_PTR_T)(0x39000048)) /* Communication data from ADM to host */ +#define ADM_UDATA7 (*(REG32_PTR_T)(0x3900004C)) /* Communication data from ADM to host */ +#define ADM_IBASE (*(REG32_PTR_T)(0x39000050)) /* Start Address for ADM Instruction Area */ +#define ADM_DBASE (*(REG32_PTR_T)(0x39000054)) /* Start Address for CalmRISC Data Area */ +#define ADM_XBASE (*(REG32_PTR_T)(0x39000058)) /* Start Address for Mac X Area */ +#define ADM_YBASE (*(REG32_PTR_T)(0x3900005C)) /* Start Address for Mac Y Area */ +#define ADM_S0BASE (*(REG32_PTR_T)(0x39000060)) /* Start Address for Sequential Block 0 Area */ +#define ADM_S1BASE (*(REG32_PTR_T)(0x39000064)) /* Start Address for Sequential Block 1 Area */ + +/* 05. CLOCK & POWER MANAGEMENT */ +#define CLKCON (*(REG32_PTR_T)(0x3C500000)) /* Clock control Register */ +#define PLL0PMS (*(REG32_PTR_T)(0x3C500004)) /* PLL PMS value Register */ +#define PLL1PMS (*(REG32_PTR_T)(0x3C500008)) /* PLL PMS value Register */ +#define PLL0LCNT (*(REG32_PTR_T)(0x3C500014)) /* PLL0 lock count register */ +#define PLL1LCNT (*(REG32_PTR_T)(0x3C500018)) /* PLL1 lock count register */ +#define PLLLOCK (*(REG32_PTR_T)(0x3C500020)) /* PLL lock status register */ +#define PLLCON (*(REG32_PTR_T)(0x3C500024)) /* PLL control register */ +#define PWRCON (*(REG32_PTR_T)(0x3C500028)) /* Clock power control register */ +#define PWRMODE (*(REG32_PTR_T)(0x3C50002C)) /* Power mode control register */ +#define SWRCON (*(REG32_PTR_T)(0x3C500030)) /* Software reset control register */ +#define RSTSR (*(REG32_PTR_T)(0x3C500034)) /* Reset status register */ +#define DSPCLKMD (*(REG32_PTR_T)(0x3C500038)) /* DSP clock mode register */ +#define CLKCON2 (*(REG32_PTR_T)(0x3C50003C)) /* clock control register 2 */ + +/* 06. INTERRUPT CONTROLLER UNIT */ +#define SRCPND (*(REG32_PTR_T)(0x39C00000)) /* Indicates the interrupt request status. */ +#define INTMOD (*(REG32_PTR_T)(0x39C00004)) /* Interrupt mode register. */ +#define INTMSK (*(REG32_PTR_T)(0x39C00008)) /* Determines which interrupt source is masked. The */ +#define PRIORITY (*(REG32_PTR_T)(0x39C0000C)) /* IRQ priority control register */ +#define INTPND (*(REG32_PTR_T)(0x39C00010)) /* Indicates the interrupt request status. */ +#define INTOFFSET (*(REG32_PTR_T)(0x39C00014)) /* Indicates the IRQ interrupt request source */ +#define EINTPOL (*(REG32_PTR_T)(0x39C00018)) /* Indicates external interrupt polarity */ +#define EINTPEND (*(REG32_PTR_T)(0x39C0001C)) /* Indicates whether external interrupts are pending. */ +#define EINTMSK (*(REG32_PTR_T)(0x39C00020)) /* Indicates whether external interrupts are masked */ + +/* 07. MEMORY INTERFACE UNIT (MIU) */ + +/* SDRAM */ +#define MIUCON (*(REG32_PTR_T)(0x38200000)) /* External Memory configuration register */ +#define MIUCOM (*(REG32_PTR_T)(0x38200004)) /* Command and status register */ +#define MIUAREF (*(REG32_PTR_T)(0x38200008)) /* Auto-refresh control register */ +#define MIUMRS (*(REG32_PTR_T)(0x3820000C)) /* SDRAM Mode Register Set Value Register */ +#define MIUSDPARA (*(REG32_PTR_T)(0x38200010)) /* SDRAM parameter register */ + +/* DDR */ +#define MEMCONF (*(REG32_PTR_T)(0x38200020)) /* External Memory configuration register */ +#define USRCMD (*(REG32_PTR_T)(0x38200024)) /* Command and Status register */ +#define AREF (*(REG32_PTR_T)(0x38200028)) /* Auto-refresh control register */ +#define MRS (*(REG32_PTR_T)(0x3820002C)) /* DRAM mode register set value register */ +#define DPARAM (*(REG32_PTR_T)(0x38200030)) /* DRAM parameter register (Unit of ‘tXXX’ : tCK */ +#define SMEMCONF (*(REG32_PTR_T)(0x38200034)) /* Static memory mode register set value register */ +#define MIUS01PARA (*(REG32_PTR_T)(0x38200038)) /* SRAM0, SRAM1 static memory parameter register (In S5L8700, SRAM0 is Nor Flash) */ +#define MIUS23PARA (*(REG32_PTR_T)(0x3820003C)) /* SRAM2 and SRAM3 static memory parameter register */ + +#define MIUORG (*(REG32_PTR_T)(0x38200040)) /* SDR/DDR selection */ +#define MIUDLYDQS (*(REG32_PTR_T)(0x38200044)) /* DQS/DQS-rst delay parameter */ +#define MIUDLYCLK (*(REG32_PTR_T)(0x38200048)) /* SDR/DDR Clock delay parameter */ +#define MIU_DSS_SEL_B (*(REG32_PTR_T)(0x3820004C)) /* SSTL2 Drive Strength parameter for Bi-direction signal */ +#define MIU_DSS_SEL_O (*(REG32_PTR_T)(0x38200050)) /* SSTL2 Drive Strength parameter for Output signal */ +#define MIU_DSS_SEL_C (*(REG32_PTR_T)(0x38200054)) /* SSTL2 Drive Strength parameter for Clock signal */ +#define PAD_DSS_SEL_NOR (*(REG32_PTR_T)(0x38200058)) /* Wide range I/O Drive Strength parameter for NOR interface */ +#define PAD_DSS_SEL_ATA (*(REG32_PTR_T)(0x3820005C)) /* Wide range I/O Drive Strength parameter for ATA interface */ +#define SSTL2_PAD_ON (*(REG32_PTR_T)(0x38200060)) /* SSTL2 pad ON/OFF select */ + +/* 08. IODMA CONTROLLER */ +#define DMABASE0 (*(REG32_PTR_T)(0x38400000)) /* Base address register for channel 0 */ +#define DMACON0 (*(REG32_PTR_T)(0x38400004)) /* Configuration register for channel 0 */ +#define DMATCNT0 (*(REG32_PTR_T)(0x38400008)) /* Transfer count register for channel 0 */ +#define DMACADDR0 (*(REG32_PTR_T)(0x3840000C)) /* Current memory address register for channel 0 */ +#define DMACTCNT0 (*(REG32_PTR_T)(0x38400010)) /* Current transfer count register for channel 0 */ +#define DMACOM0 (*(REG32_PTR_T)(0x38400014)) /* Channel 0 command register */ +#define DMANOFF0 (*(REG32_PTR_T)(0x38400018)) /* Channel 0 offset2 register */ +#define DMABASE1 (*(REG32_PTR_T)(0x38400020)) /* Base address register for channel 1 */ +#define DMACON1 (*(REG32_PTR_T)(0x38400024)) /* Configuration register for channel 1 */ +#define DMATCNT1 (*(REG32_PTR_T)(0x38400028)) /* Transfer count register for channel 1 */ +#define DMACADDR1 (*(REG32_PTR_T)(0x3840002C)) /* Current memory address register for channel 1 */ +#define DMACTCNT1 (*(REG32_PTR_T)(0x38400030)) /* Current transfer count register for channel 1 */ +#define DMACOM1 (*(REG32_PTR_T)(0x38400034)) /* Channel 1 command register */ +#define DMABASE2 (*(REG32_PTR_T)(0x38400040)) /* Base address register for channel 2 */ +#define DMACON2 (*(REG32_PTR_T)(0x38400044)) /* Configuration register for channel 2 */ +#define DMATCNT2 (*(REG32_PTR_T)(0x38400048)) /* Transfer count register for channel 2 */ +#define DMACADDR2 (*(REG32_PTR_T)(0x3840004C)) /* Current memory address register for channel 2 */ +#define DMACTCNT2 (*(REG32_PTR_T)(0x38400050)) /* Current transfer count register for channel 2 */ +#define DMACOM2 (*(REG32_PTR_T)(0x38400054)) /* Channel 2 command register */ +#define DMABASE3 (*(REG32_PTR_T)(0x38400060)) /* Base address register for channel 3 */ +#define DMACON3 (*(REG32_PTR_T)(0x38400064)) /* Configuration register for channel 3 */ +#define DMATCNT3 (*(REG32_PTR_T)(0x38400068)) /* Transfer count register for channel 3 */ +#define DMACADDR3 (*(REG32_PTR_T)(0x3840006C)) /* Current memory address register for channel 3 */ +#define DMACTCNT3 (*(REG32_PTR_T)(0x38400070)) /* Current transfer count register for channel 3 */ +#define DMACOM3 (*(REG32_PTR_T)(0x38400074)) /* Channel 3 command register */ +#define DMAALLST (*(REG32_PTR_T)(0x38400100)) /* All channel status register */ + +/* 10. REAL TIMER CLOCK (RTC) */ +#define RTCCON (*(REG32_PTR_T)(0x3D200000)) /* RTC Control Register */ +#define RTCRST (*(REG32_PTR_T)(0x3D200004)) /* RTC Round Reset Register */ +#define RTCALM (*(REG32_PTR_T)(0x3D200008)) /* RTC Alarm Control Register */ +#define ALMSEC (*(REG32_PTR_T)(0x3D20000C)) /* Alarm Second Data Register */ +#define ALMMIN (*(REG32_PTR_T)(0x3D200010)) /* Alarm Minute Data Register */ +#define ALMHOUR (*(REG32_PTR_T)(0x3D200014)) /* Alarm Hour Data Register */ +#define ALMDATE (*(REG32_PTR_T)(0x3D200018)) /* Alarm Date Data Register */ +#define ALMDAY (*(REG32_PTR_T)(0x3D20001C)) /* Alarm Day of Week Data Register */ +#define ALMMON (*(REG32_PTR_T)(0x3D200020)) /* Alarm Month Data Register */ +#define ALMYEAR (*(REG32_PTR_T)(0x3D200024)) /* Alarm Year Data Register */ +#define BCDSEC (*(REG32_PTR_T)(0x3D200028)) /* BCD Second Register */ +#define BCDMIN (*(REG32_PTR_T)(0x3D20002C)) /* BCD Minute Register */ +#define BCDHOUR (*(REG32_PTR_T)(0x3D200030)) /* BCD Hour Register */ +#define BCDDATE (*(REG32_PTR_T)(0x3D200034)) /* BCD Date Register */ +#define BCDDAY (*(REG32_PTR_T)(0x3D200038)) /* BCD Day of Week Register */ +#define BCDMON (*(REG32_PTR_T)(0x3D20003C)) /* BCD Month Register */ +#define BCDYEAR (*(REG32_PTR_T)(0x3D200040)) /* BCD Year Register */ +#define RTCIM (*(REG32_PTR_T)(0x3D200044)) /* RTC Interrupt Mode Register */ +#define RTCPEND (*(REG32_PTR_T)(0x3D200048)) /* RTC Interrupt Pending Register */ + +/* 09. WATCHDOG TIMER*/ +#define WDTCON (*(REG32_PTR_T)(0x3C800000)) /* Control Register */ +#define WDTCNT (*(REG32_PTR_T)(0x3C800004)) /* 11-bits internal counter */ + +/* 11. 16 BIT TIMER */ +#define TACON (*(REG32_PTR_T)(0x3C700000)) /* Control Register for timer A */ +#define TACMD (*(REG32_PTR_T)(0x3C700004)) /* Command Register for timer A */ +#define TADATA0 (*(REG32_PTR_T)(0x3C700008)) /* Data0 Register */ +#define TADATA1 (*(REG32_PTR_T)(0x3C70000C)) /* Data1 Register */ +#define TAPRE (*(REG32_PTR_T)(0x3C700010)) /* Pre-scale register */ +#define TACNT (*(REG32_PTR_T)(0x3C700014)) /* Counter register */ +#define TBCON (*(REG32_PTR_T)(0x3C700020)) /* Control Register for timer B */ +#define TBCMD (*(REG32_PTR_T)(0x3C700024)) /* Command Register for timer B */ +#define TBDATA0 (*(REG32_PTR_T)(0x3C700028)) /* Data0 Register */ +#define TBDATA1 (*(REG32_PTR_T)(0x3C70002C)) /* Data1 Register */ +#define TBPRE (*(REG32_PTR_T)(0x3C700030)) /* Pre-scale register */ +#define TBCNT (*(REG32_PTR_T)(0x3C700034)) /* Counter register */ +#define TCCON (*(REG32_PTR_T)(0x3C700040)) /* Control Register for timer C */ +#define TCCMD (*(REG32_PTR_T)(0x3C700044)) /* Command Register for timer C */ +#define TCDATA0 (*(REG32_PTR_T)(0x3C700048)) /* Data0 Register */ +#define TCDATA1 (*(REG32_PTR_T)(0x3C70004C)) /* Data1 Register */ +#define TCPRE (*(REG32_PTR_T)(0x3C700050)) /* Pre-scale register */ +#define TCCNT (*(REG32_PTR_T)(0x3C700054)) /* Counter register */ +#define TDCON (*(REG32_PTR_T)(0x3C700060)) /* Control Register for timer D */ +#define TDCMD (*(REG32_PTR_T)(0x3C700064)) /* Command Register for timer D */ +#define TDDATA0 (*(REG32_PTR_T)(0x3C700068)) /* Data0 Register */ +#define TDDATA1 (*(REG32_PTR_T)(0x3C70006C)) /* Data1 Register */ +#define TDPRE (*(REG32_PTR_T)(0x3C700070)) /* Pre-scale register */ +#define TDCNT (*(REG32_PTR_T)(0x3C700074)) /* Counter register */ + +/* 12. NAND FLASH CONTROLER */ +#define FMCTRL0 (*(REG32_PTR_T)(0x3C200000)) /* Control Register0 */ +#define FMCTRL1 (*(REG32_PTR_T)(0x3C200004)) /* Control Register1 */ +#define FMCMD (*(REG32_PTR_T)(0x3C200008)) /* Command Register */ +#define FMADDR0 (*(REG32_PTR_T)(0x3C20000C)) /* Address Register0 */ +#define FMADDR1 (*(REG32_PTR_T)(0x3C200010)) /* Address Register1 */ +#define FMADDR2 (*(REG32_PTR_T)(0x3C200014)) /* Address Register2 */ +#define FMADDR3 (*(REG32_PTR_T)(0x3C200018)) /* Address Register3 */ +#define FMADDR4 (*(REG32_PTR_T)(0x3C20001C)) /* Address Register4 */ +#define FMADDR5 (*(REG32_PTR_T)(0x3C200020)) /* Address Register5 */ +#define FMADDR6 (*(REG32_PTR_T)(0x3C200024)) /* Address Register6 */ +#define FMADDR7 (*(REG32_PTR_T)(0x3C200028)) /* Address Register7 */ +#define FMANUM (*(REG32_PTR_T)(0x3C20002C)) /* Address Counter Register */ +#define FMDNUM (*(REG32_PTR_T)(0x3C200030)) /* Data Counter Register */ +#define FMDATAW0 (*(REG32_PTR_T)(0x3C200034)) /* Write Data Register0 */ +#define FMDATAW1 (*(REG32_PTR_T)(0x3C200038)) /* Write Data Register1 */ +#define FMDATAW2 (*(REG32_PTR_T)(0x3C20003C)) /* Write Data Register2 */ +#define FMDATAW3 (*(REG32_PTR_T)(0x3C200040)) /* Write Data Register3 */ +#define FMCSTAT (*(REG32_PTR_T)(0x3C200048)) /* Status Register */ +#define FMSYND0 (*(REG32_PTR_T)(0x3C20004C)) /* Hamming Syndrome0 */ +#define FMSYND1 (*(REG32_PTR_T)(0x3C200050)) /* Hamming Syndrome1 */ +#define FMSYND2 (*(REG32_PTR_T)(0x3C200054)) /* Hamming Syndrome2 */ +#define FMSYND3 (*(REG32_PTR_T)(0x3C200058)) /* Hamming Syndrome3 */ +#define FMSYND4 (*(REG32_PTR_T)(0x3C20005C)) /* Hamming Syndrome4 */ +#define FMSYND5 (*(REG32_PTR_T)(0x3C200060)) /* Hamming Syndrome5 */ +#define FMSYND6 (*(REG32_PTR_T)(0x3C200064)) /* Hamming Syndrome6 */ +#define FMSYND7 (*(REG32_PTR_T)(0x3C200068)) /* Hamming Syndrome7 */ +#define FMFIFO (*(REG32_PTR_T)(0x3C200080)) /* WRITE/READ FIFO FIXME */ +#define RSCRTL (*(REG32_PTR_T)(0x3C200100)) /* Reed-Solomon Control Register */ +#define RSPaity0_0 (*(REG32_PTR_T)(0x3C200110)) /* On-the-fly Parity Register0[31:0] */ +#define RSPaity0_1 (*(REG32_PTR_T)(0x3C200114)) /* On-the-fly Parity Register0[63:32] */ +#define RSPaity0_2 (*(REG32_PTR_T)(0x3C200118)) /* On-the-fly Parity Register0[71:64] */ +#define RSPaity1_0 (*(REG32_PTR_T)(0x3C200120)) /* On-the-fly Parity Register1[31:0] */ +#define RSPaity1_1 (*(REG32_PTR_T)(0x3C200124)) /* On-the-fly Parity Register1[63:32] */ +#define RSPaity1_2 (*(REG32_PTR_T)(0x3C200128)) /* On-the-fly Parity Register1[71:64] */ +#define RSPaity2_0 (*(REG32_PTR_T)(0x3C200130)) /* On-the-fly Parity Register2[31:0] */ +#define RSPaity2_1 (*(REG32_PTR_T)(0x3C200134)) /* On-the-fly Parity Register2[63:32] */ +#define RSPaity2_2 (*(REG32_PTR_T)(0x3C200138)) /* On-the-fly Parity Register2[71:64] */ +#define RSPaity3_0 (*(REG32_PTR_T)(0x3C200140)) /* On-the-fly Parity Register3[31:0] */ +#define RSPaity3_1 (*(REG32_PTR_T)(0x3C200144)) /* On-the-fly Parity Register3[63:32] */ +#define RSPaity3_2 (*(REG32_PTR_T)(0x3C200148)) /* On-the-fly Parity Register3[71:64] */ +#define RSSynd0_0 (*(REG32_PTR_T)(0x3C200150)) /* On-the-fly Synd Register0[31:0] */ +#define RSSynd0_1 (*(REG32_PTR_T)(0x3C200154)) /* On-the-fly Synd Register0[63:32] */ +#define RSSynd0_2 (*(REG32_PTR_T)(0x3C200158)) /* On-the-fly Synd Register0[71:64] */ +#define RSSynd1_0 (*(REG32_PTR_T)(0x3C200160)) /* On-the-fly Synd Register1[31:0] */ +#define RSSynd1_1 (*(REG32_PTR_T)(0x3C200164)) /* On-the-fly Synd Register1[63:32] */ +#define RSSynd1_2 (*(REG32_PTR_T)(0x3C200168)) /* On-the-fly Synd Register1[71:64] */ +#define RSSynd2_0 (*(REG32_PTR_T)(0x3C200170)) /* On-the-fly Synd Register2[31:0] */ +#define RSSynd2_1 (*(REG32_PTR_T)(0x3C200174)) /* On-the-fly Synd Register2[63:32] */ +#define RSSynd2_2 (*(REG32_PTR_T)(0x3C200178)) /* On-the-fly Synd Register2[71:64] */ +#define RSSynd3_0 (*(REG32_PTR_T)(0x3C200180)) /* On-the-fly Synd Register3[31:0] */ +#define RSSynd3_1 (*(REG32_PTR_T)(0x3C200184)) /* On-the-fly Synd Register3[63:32] */ +#define RSSynd3_2 (*(REG32_PTR_T)(0x3C200188)) /* On-the-fly Synd Register3[71:64] */ +#define FlagSynd (*(REG32_PTR_T)(0x3C200190)) /* On-the-fly ECC Result Flag */ + +/* 13. SECURE DIGITAL CARD INTERFACE (SDCI) */ +#define SDCI_CTRL (*(REG32_PTR_T)(0x3C300000)) /* Control Register */ +#define SDCI_DCTRL (*(REG32_PTR_T)(0x3C300004)) /* Data Control Register */ +#define SDCI_CMD (*(REG32_PTR_T)(0x3C300008)) /* Command Register */ +#define SDCI_ARGU (*(REG32_PTR_T)(0x3C30000C)) /* Argument Register */ +#define SDCI_STATE (*(REG32_PTR_T)(0x3C300010)) /* State Register */ +#define SDCI_STAC (*(REG32_PTR_T)(0x3C300014)) /* Status Clear Register */ +#define SDCI_DSTA (*(REG32_PTR_T)(0x3C300018)) /* Data Status Register */ +#define SDCI_FSTA (*(REG32_PTR_T)(0x3C30001C)) /* FIFO Status Register */ +#define SDCI_RESP0 (*(REG32_PTR_T)(0x3C300020)) /* Response0 Register */ +#define SDCI_RESP1 (*(REG32_PTR_T)(0x3C300024)) /* Response1 Register */ +#define SDCI_RESP2 (*(REG32_PTR_T)(0x3C300028)) /* Response2 Register */ +#define SDCI_RESP3 (*(REG32_PTR_T)(0x3C30002C)) /* Response3 Register */ +#define SDCI_CLKDIV (*(REG32_PTR_T)(0x3C300030)) /* Clock Divider Register */ +#define SDIO_CSR (*(REG32_PTR_T)(0x3C300034)) /* SDIO Control & Status Register */ +#define SDIO_IRQ (*(REG32_PTR_T)(0x3C300038)) /* Interrupt Source Register */ + +/* 14. MEMORY STICK HOST CONTROLLER */ +#define MSPRE (*(REG32_PTR_T)(0x3C600000)) /* Prescaler Register */ +#define MSINTEN (*(REG32_PTR_T)(0x3C600004)) /* Interrupt Enable Register */ +#define MSCMD (*(REG32_PTR_T)(0x3C601000)) /* Command Register */ +#define MSFIFO (*(REG32_PTR_T)(0x3C601008)) /* Receive/Transmit Register */ +#define MSPP (*(REG32_PTR_T)(0x3C601010)) /* Parallel Port Control/Data Register */ +#define MSCTRL2 (*(REG32_PTR_T)(0x3C601014)) /* Control Register 2 */ +#define MSACD (*(REG32_PTR_T)(0x3C601018)) /* ACD Command Register */ + +/* 15. SPDIF TRANSMITTER (SPDIFOUT) */ +#define SPDCLKCON (*(REG32_PTR_T)(0x3CB00000)) /* Clock Control Register */ +#define SPDCON (*(REG32_PTR_T)(0x3CB00004)) /* Control Register 0020 */ +#define SPDBSTAS (*(REG32_PTR_T)(0x3CB00008)) /* Burst Status Register */ +#define SPDCSTAS (*(REG32_PTR_T)(0x3CB0000C)) /* Channel Status Register 0x2000 8000 */ +#define SPDDAT (*(REG32_PTR_T)(0x3CB00010)) /* SPDIFOUT Data Buffer */ +#define SPDCNT (*(REG32_PTR_T)(0x3CB00014)) /* Repetition Count Register */ + +/* 16. REED-SOLOMON ECC CODEC */ +#define DATA_PTR (*(REG32_PTR_T)(0x39E00004)) /* Data Area Start Pointer */ +#define SPARE_PTR (*(REG32_PTR_T)(0x39E00008)) /* Spare Area Start Pointer */ +#define ECC_CTRL (*(REG32_PTR_T)(0x39E0000C)) /* ECC Control Register */ +#define ECC_RESULT (*(REG32_PTR_T)(0x39E00010)) /* ECC Result */ +#define ECC_EVAL0 (*(REG32_PTR_T)(0x39E00020)) /* Error Eval0 Poly */ +#define ECC_EVAL1 (*(REG32_PTR_T)(0x39E00024)) /* Error Eval1 Poly */ +#define ECC_LOC0 (*(REG32_PTR_T)(0x39E00028)) /* Error Loc0 Poly */ +#define ECC_LOC1 (*(REG32_PTR_T)(0x39E0002C)) /* Error Loc1 Poly */ +#define PARITY0 (*(REG32_PTR_T)(0x39E00030)) /* Encode Parity0 Poly */ +#define PARITY1 (*(REG32_PTR_T)(0x39E00034)) /* Encode Pariyt1 Poly */ +#define PARITY2 (*(REG32_PTR_T)(0x39E00038)) /* Encode Parity2 Poly */ +#define INT_CLR (*(REG32_PTR_T)(0x39E00040)) /* Interrupt Clear Register */ +#define SYND0 (*(REG32_PTR_T)(0x39E00044)) /* Syndrom0 Poly */ +#define SYND1 (*(REG32_PTR_T)(0x39E00048)) /* Syndrom1 Poly */ +#define SYND2 (*(REG32_PTR_T)(0x39E0004C)) /* Syndrom2 Poly */ + +/* 17. IIS Tx/Rx INTERFACE */ +#define I2SCLKCON (*(REG32_PTR_T)(0x3CA00000)) /* Clock Control Register */ +#define I2STXCON (*(REG32_PTR_T)(0x3CA00004)) /* Tx configuration Register */ +#define I2STXCOM (*(REG32_PTR_T)(0x3CA00008)) /* Tx command Register */ +#define I2STXDB0 (*(REG32_PTR_T)(0x3CA00010)) /* Tx data buffer */ +#define I2SRXCON (*(REG32_PTR_T)(0x3CA00030)) /* Rx configuration Register */ +#define I2SRXCOM (*(REG32_PTR_T)(0x3CA00034)) /* Rx command Register */ +#define I2SRXDB (*(REG32_PTR_T)(0x3CA00038)) /* Rx data buffer */ +#define I2SSTATUS (*(REG32_PTR_T)(0x3CA0003C)) /* status register */ + +/* 18. IIC BUS INTERFACE */ +#define IICCON (*(REG32_PTR_T)(0x3C900000)) /* Control Register */ +#define IICSTAT (*(REG32_PTR_T)(0x3C900004)) /* Control/Status Register */ +#define IICADD (*(REG32_PTR_T)(0x3C900008)) /* Bus Address Register */ +#define IICDS (*(REG32_PTR_T)(0x3C90000C)) + +/* 19. SPI (SERIAL PERHIPERAL INTERFACE) */ +#define SPCLKCON (*(REG32_PTR_T)(0x3CD00000)) /* Clock Control Register */ +#define SPCON (*(REG32_PTR_T)(0x3CD00004)) /* Control Register */ +#define SPSTA (*(REG32_PTR_T)(0x3CD00008)) /* Status Register */ +#define SPPIN (*(REG32_PTR_T)(0x3CD0000C)) /* Pin Control Register */ +#define SPTDAT (*(REG32_PTR_T)(0x3CD00010)) /* Tx Data Register */ +#define SPRDAT (*(REG32_PTR_T)(0x3CD00014)) /* Rx Data Register */ +#define SPPRE (*(REG32_PTR_T)(0x3CD00018)) /* Baud Rate Prescaler Register */ + +/* 20. ADC CONTROLLER */ +#define ADCCON (*(REG32_PTR_T)(0x3CE00000)) /* ADC Control Register */ +#define ADCTSC (*(REG32_PTR_T)(0x3CE00004)) /* ADC Touch Screen Control Register */ +#define ADCDLY (*(REG32_PTR_T)(0x3CE00008)) /* ADC Start or Interval Delay Register */ +#define ADCDAT0 (*(REG32_PTR_T)(0x3CE0000C)) /* ADC Conversion Data Register */ +#define ADCDAT1 (*(REG32_PTR_T)(0x3CE00010)) /* ADC Conversion Data Register */ +#define ADCUPDN (*(REG32_PTR_T)(0x3CE00014)) /* Stylus Up or Down Interrpt Register */ + +/* 21. USB 2.0 FUNCTION CONTROLER SPECIAL REGISTER */ +#define IR (*(REG32_PTR_T)(0x38800000)) /* Index Register */ +#define EIR (*(REG32_PTR_T)(0x38800004)) /* Endpoint Interrupt Register */ +#define EIER (*(REG32_PTR_T)(0x38800008)) /* Endpoint Interrupt Enable Register */ +#define FAR (*(REG32_PTR_T)(0x3880000C)) /* Function Address Register */ +#define FNR (*(REG32_PTR_T)(0x38800010)) /* Frame Number Register */ +#define EDR (*(REG32_PTR_T)(0x38800014)) /* Endpoint Direction Register */ +#define TR (*(REG32_PTR_T)(0x38800018)) /* Test Register */ +#define SSR (*(REG32_PTR_T)(0x3880001C)) /* System Status Register */ +#define SCR (*(REG32_PTR_T)(0x38800020)) /* System Control Register */ +#define EP0SR (*(REG32_PTR_T)(0x38800024)) /* EP0 Status Register */ +#define EP0CR (*(REG32_PTR_T)(0x38800028)) /* EP0 Control Register */ +#define ESR (*(REG32_PTR_T)(0x3880002C)) /* Endpoints Status Register */ +#define ECR (*(REG32_PTR_T)(0x38800030)) /* Endpoints Control Register */ +#define BRCR (*(REG32_PTR_T)(0x38800034)) /* Byte Read Count Register */ +#define BWCR (*(REG32_PTR_T)(0x38800038)) /* Byte Write Count Register */ +#define MPR (*(REG32_PTR_T)(0x3880003C)) /* Max Packet Register */ +#define MCR (*(REG32_PTR_T)(0x38800040)) /* Master Control Register */ +#define MTCR (*(REG32_PTR_T)(0x38800044)) /* Master Transfer Counter Register */ +#define MFCR (*(REG32_PTR_T)(0x38800048)) /* Master FIFO Counter Register */ +#define MTTCR1 (*(REG32_PTR_T)(0x3880004C)) /* Master Total Transfer Counter1 Register */ +#define MTTCR2 (*(REG32_PTR_T)(0x38800050)) /* Master Total Transfer Counter2 Register */ +#define EP0BR (*(REG32_PTR_T)(0x38800060)) /* EP0 Buffer Register */ +#define EP1BR (*(REG32_PTR_T)(0x38800064)) /* EP1 Buffer Register */ +#define EP2BR (*(REG32_PTR_T)(0x38800068)) /* EP2 Buffer Register */ +#define EP3BR (*(REG32_PTR_T)(0x3880006C)) /* EP3 Buffer Register */ +#define EP4BR (*(REG32_PTR_T)(0x38800070)) /* EP4 Buffer Register */ +#define EP5BR (*(REG32_PTR_T)(0x38800074)) /* EP5 Buffer Register */ +#define EP6BR (*(REG32_PTR_T)(0x38800078)) /* EP6 Buffer Register */ +#define MICR (*(REG32_PTR_T)(0x38800084)) /* Master Interface Counter Register */ +#define MBAR1 (*(REG32_PTR_T)(0x38800088)) /* Memory Base Address Register1 */ +#define MBAR2 (*(REG32_PTR_T)(0x3880008C)) /* Memory Base Address Register2 */ +#define MCAR1 (*(REG32_PTR_T)(0x38800094)) /* Memory Current Address Register1 */ +#define MCAR2 (*(REG32_PTR_T)(0x38800098)) /* Memory Current Address Register2 */ + +/* 22. USB 1.1 HOST CONTROLER SPECIAL REGISTER */ +#define HcRevision (*(REG32_PTR_T)(0x38600000)) +#define HcControl (*(REG32_PTR_T)(0x38600004)) +#define HcCommandStatus (*(REG32_PTR_T)(0x38600008)) +#define HcInterruptStatus (*(REG32_PTR_T)(0x3860000C)) +#define HcInterruptEnable (*(REG32_PTR_T)(0x38600010)) +#define HcInterruptDisable (*(REG32_PTR_T)(0x38600014)) +#define HcHCCA (*(REG32_PTR_T)(0x38600018)) +#define HcPeriodCurrentED (*(REG32_PTR_T)(0x3860001C)) +#define HcControlHeadED (*(REG32_PTR_T)(0x38600020)) +#define HcControlCurrentED (*(REG32_PTR_T)(0x38600024)) +#define HcBulkHeadED (*(REG32_PTR_T)(0x38600028)) +#define HcBulkCurrentED (*(REG32_PTR_T)(0x3860002C)) +#define HcDoneHead (*(REG32_PTR_T)(0x38600030)) +#define HcFmInterval (*(REG32_PTR_T)(0x38600034)) +#define HcFmRemaining (*(REG32_PTR_T)(0x38600038)) +#define HcFmNumber (*(REG32_PTR_T)(0x3860003C)) +#define HcPeriodicStart (*(REG32_PTR_T)(0x38600040)) +#define HcLSThreshold (*(REG32_PTR_T)(0x38600044)) +#define HcRhDescriptorA (*(REG32_PTR_T)(0x38600048)) +#define HcRhDescriptorB (*(REG32_PTR_T)(0x3860004C)) +#define HcRhStatus (*(REG32_PTR_T)(0x38600050)) +#define HcRhPortStatus (*(REG32_PTR_T)(0x38600054)) + +/* 23. USB 2.0 PHY CONTROL */ +#define PHYCTRL (*(REG32_PTR_T)(0x3C400000)) /* USB2.0 PHY Control Register */ +#define PHYPWR (*(REG32_PTR_T)(0x3C400004)) /* USB2.0 PHY Power Control Register */ +#define URSTCON (*(REG32_PTR_T)(0x3C400008)) /* USB Reset Control Register */ +#define UCLKCON (*(REG32_PTR_T)(0x3C400010)) /* USB Clock Control Register */ + +/* 24. GPIO PORT CONTROLL */ +#define PCON0 (*(REG32_PTR_T)(0x3CF00000)) /* Configures the pins of port 0 */ +#define PDAT0 (*(REG32_PTR_T)(0x3CF00004)) /* The data register for port 0 */ +#define PCON1 (*(REG32_PTR_T)(0x3CF00010)) /* Configures the pins of port 0 */ +#define PDAT1 (*(REG32_PTR_T)(0x3CF00014)) /* The data register for port 0 */ +#define PCON2 (*(REG32_PTR_T)(0x3CF00020)) /* Configures the pins of port 0 */ +#define PDAT2 (*(REG32_PTR_T)(0x3CF00024)) /* The data register for port 0 */ +#define PCON3 (*(REG32_PTR_T)(0x3CF00030)) /* Configures the pins of port 0 */ +#define PDAT3 (*(REG32_PTR_T)(0x3CF00034)) /* The data register for port 0 */ +#define PCON4 (*(REG32_PTR_T)(0x3CF00040)) /* Configures the pins of port 0 */ +#define PDAT4 (*(REG32_PTR_T)(0x3CF00044)) /* The data register for port 0 */ +#define PCON5 (*(REG32_PTR_T)(0x3CF00050)) /* Configures the pins of port 0 */ +#define PDAT5 (*(REG32_PTR_T)(0x3CF00054)) /* The data register for port 0 */ +#define PCON6 (*(REG32_PTR_T)(0x3CF00060)) /* Configures the pins of port 0 */ +#define PDAT6 (*(REG32_PTR_T)(0x3CF00064)) /* The data register for port 0 */ +#define PCON7 (*(REG32_PTR_T)(0x3CF00070)) /* Configures the pins of port 0 */ +#define PDAT7 (*(REG32_PTR_T)(0x3CF00074)) /* The data register for port 0 */ +#define PCON10 (*(REG32_PTR_T)(0x3CF000A0)) /* Configures the pins of port 0 */ +#define PDAT10 (*(REG32_PTR_T)(0x3CF000A4)) /* The data register for port 0 */ +#define PCON_ASRAM (*(REG32_PTR_T)(0x3CF000F0)) /* Configures the pins of port nor flash */ +#define PCON_SDRAM (*(REG32_PTR_T)(0x3CF000F4)) /* Configures the pins of port sdram */ +#define PCON11 (*(REG32_PTR_T)(0x3CF000F8)) /* Configures the pins of port 11 */ +#define PDAT11 (*(REG32_PTR_T)(0x3CF000FC)) /* The data register for port 11 */ + +/* 25. UART */ + +/* UART 0 */ +#define ULCON0 (*(REG32_PTR_T)(0x3CC00000)) /* Line Control Register */ +#define UCON0 (*(REG32_PTR_T)(0x3CC00004)) /* Control Register */ +#define UFCON0 (*(REG32_PTR_T)(0x3CC00008)) /* FIFO Control Register */ +#define UMCON0 (*(REG32_PTR_T)(0x3CC0000C)) /* Modem Control Register */ +#define UTRSTAT0 (*(REG32_PTR_T)(0x3CC00010)) /* Tx/Rx Status Register */ +#define UERSTAT0 (*(REG32_PTR_T)(0x3CC00014)) /* Rx Error Status Register */ +#define UFSTAT0 (*(REG32_PTR_T)(0x3CC00018)) /* FIFO Status Register */ +#define UMSTAT0 (*(REG32_PTR_T)(0x3CC0001C)) /* Modem Status Register */ +#define UTXH0 (*(REG32_PTR_T)(0x3CC00020)) /* Transmit Buffer Register */ +#define URXH0 (*(REG32_PTR_T)(0x3CC00024)) /* Receive Buffer Register */ +#define UBRDIV0 (*(REG32_PTR_T)(0x3CC00028)) /* Baud Rate Divisor Register */ + +/* UART 1*/ +#define ULCON1 (*(REG32_PTR_T)(0x3CC08000)) /* Line Control Register */ +#define UCON1 (*(REG32_PTR_T)(0x3CC08004)) /* Control Register */ +#define UFCON1 (*(REG32_PTR_T)(0x3CC08008)) /* FIFO Control Register */ +#define UMCON1 (*(REG32_PTR_T)(0x3CC0800C)) /* Modem Control Register */ +#define UTRSTAT1 (*(REG32_PTR_T)(0x3CC08010)) /* Tx/Rx Status Register */ +#define UERSTAT1 (*(REG32_PTR_T)(0x3CC08014)) /* Rx Error Status Register */ +#define UFSTAT1 (*(REG32_PTR_T)(0x3CC08018)) /* FIFO Status Register */ +#define UMSTAT1 (*(REG32_PTR_T)(0x3CC0801C)) /* Modem Status Register */ +#define UTXH1 (*(REG32_PTR_T)(0x3CC08020)) /* Transmit Buffer Register */ +#define URXH1 (*(REG32_PTR_T)(0x3CC08024)) /* Receive Buffer Register */ +#define UBRDIV1 (*(REG32_PTR_T)(0x3CC08028)) /* Baud Rate Divisor Register */ + +/* 26. LCD INTERFACE CONTROLLER */ +#define LCD_CON (*(REG32_PTR_T)(0x3C100000)) /* Control register. */ +#define LCD_WCMD (*(REG32_PTR_T)(0x3C100004)) /* Write command register. */ +#define LCD_RCMD (*(REG32_PTR_T)(0x3C10000C)) /* Read command register. */ +#define LCD_RDATA (*(REG32_PTR_T)(0x3C100010)) /* Read data register. */ +#define LCD_DBUFF (*(REG32_PTR_T)(0x3C100014)) /* Read Data buffer */ +#define LCD_INTCON (*(REG32_PTR_T)(0x3C100018)) /* Interrupt control register */ +#define LCD_STATUS (*(REG32_PTR_T)(0x3C10001C)) /* LCD Interface status 0106 */ +#define LCD_PHTIME (*(REG32_PTR_T)(0x3C100020)) /* Phase time register 0060 */ +#define LCD_RST_TIME (*(REG32_PTR_T)(0x3C100024)) /* Reset active period 07FF */ +#define LCD_DRV_RST (*(REG32_PTR_T)(0x3C100028)) /* Reset drive signal */ +#define LCD_WDATA (*(REG32_PTR_T)(0x3C100040)) /* Write data register FIXME */ + +/* 27. CLCD CONTROLLER */ +#define LCDCON1 (*(REG32_PTR_T)(0x39200000)) /* LCD control 1 register */ +#define LCDCON2 (*(REG32_PTR_T)(0x39200004)) /* LCD control 2 register */ +#define LCDTCON1 (*(REG32_PTR_T)(0x39200008)) /* LCD time control 1 register */ +#define LCDTCON2 (*(REG32_PTR_T)(0x3920000C)) /* LCD time control 2 register */ +#define LCDTCON3 (*(REG32_PTR_T)(0x39200010)) /* LCD time control 3 register */ +#define LCDOSD1 (*(REG32_PTR_T)(0x39200014)) /* LCD OSD control 1 register */ +#define LCDOSD2 (*(REG32_PTR_T)(0x39200018)) /* LCD OSD control 2 register */ +#define LCDOSD3 (*(REG32_PTR_T)(0x3920001C)) /* LCD OSD control 3 register */ +#define LCDB1SADDR1 (*(REG32_PTR_T)(0x39200020)) /* Frame buffer start address register for Back-Ground buffer 1 */ +#define LCDB2SADDR1 (*(REG32_PTR_T)(0x39200024)) /* Frame buffer start address register for Back-Ground buffer 2 */ +#define LCDF1SADDR1 (*(REG32_PTR_T)(0x39200028)) /* Frame buffer start address register for Fore-Ground (OSD) buffer 1 */ +#define LCDF2SADDR1 (*(REG32_PTR_T)(0x3920002C)) /* Frame buffer start address register for Fore-Ground (OSD) buffer 2 */ +#define LCDB1SADDR2 (*(REG32_PTR_T)(0x39200030)) /* Frame buffer end address register for Back-Ground buffer 1 */ +#define LCDB2SADDR2 (*(REG32_PTR_T)(0x39200034)) /* Frame buffer end address register for Back-Ground buffer 2 */ +#define LCDF1SADDR2 (*(REG32_PTR_T)(0x39200038)) /* Frame buffer end address register for Fore-Ground (OSD) buffer 1 */ +#define LCDF2SADDR2 (*(REG32_PTR_T)(0x3920003C)) /* Frame buffer end address register for Fore-Ground (OSD) buffer 2 */ +#define LCDB1SADDR3 (*(REG32_PTR_T)(0x39200040)) /* Virtual screen address set for Back-Ground buffer 1 */ +#define LCDB2SADDR3 (*(REG32_PTR_T)(0x39200044)) /* Virtual screen address set for Back-Ground buffer 2 */ +#define LCDF1SADDR3 (*(REG32_PTR_T)(0x39200048)) /* Virtual screen address set for Fore-Ground(OSD) buffer 1 */ +#define LCDF2SADDR3 (*(REG32_PTR_T)(0x3920004C)) /* Virtual screen address set for Fore-Ground(OSD) buffer 2 */ +#define LCDINTCON (*(REG32_PTR_T)(0x39200050)) /* Indicate the LCD interrupt control register */ +#define KEYCON (*(REG32_PTR_T)(0x39200054)) /* Color key control register */ +#define COLVAL (*(REG32_PTR_T)(0x39200058)) /* Color key value ( transparent value) register */ +#define BGCON (*(REG32_PTR_T)(0x3920005C)) /* Back-Ground color control */ +#define FGCON (*(REG32_PTR_T)(0x39200060)) /* Fore-Ground color control */ +#define DITHMODE (*(REG32_PTR_T)(0x39200064)) /* Dithering mode register. */ + +/* 28. ATA CONTROLLER */ +#define ATA_CONTROL (*(REG32_PTR_T)(0x38E00000)) /* Enable and clock down status */ +#define ATA_STATUS (*(REG32_PTR_T)(0x38E00004)) /* Status */ +#define ATA_COMMAND (*(REG32_PTR_T)(0x38E00008)) /* Command */ +#define ATA_SWRST (*(REG32_PTR_T)(0x38E0000C)) /* Software reset */ +#define ATA_IRQ (*(REG32_PTR_T)(0x38E00010)) /* Interrupt sources */ +#define ATA_IRQ_MASK (*(REG32_PTR_T)(0x38E00014)) /* Interrupt mask */ +#define ATA_CFG (*(REG32_PTR_T)(0x38E00018)) /* Configuration for ATA interface */ +#define ATA_PIO_TIME (*(REG32_PTR_T)(0x38E0002C)) /* PIO timing */ +#define ATA_UDMA_TIME (*(REG32_PTR_T)(0x38E00030)) /* UDMA timing */ +#define ATA_XFR_NUM (*(REG32_PTR_T)(0x38E00034)) /* Transfer number */ +#define ATA_XFR_CNT (*(REG32_PTR_T)(0x38E00038)) /* Current transfer count */ +#define ATA_TBUF_START (*(REG32_PTR_T)(0x38E0003C)) /* Start address of track buffer */ +#define ATA_TBUF_SIZE (*(REG32_PTR_T)(0x38E00040)) /* Size of track buffer */ +#define ATA_SBUF_START (*(REG32_PTR_T)(0x38E00044)) /* Start address of Source buffer1 */ +#define ATA_SBUF_SIZE (*(REG32_PTR_T)(0x38E00048)) /* Size of source buffer1 */ +#define ATA_CADR_TBUF (*(REG32_PTR_T)(0x38E0004C)) /* Current write address of track buffer */ +#define ATA_CADR_SBUF (*(REG32_PTR_T)(0x38E00050)) /* Current read address of source buffer */ +#define ATA_PIO_DTR (*(REG32_PTR_T)(0x38E00054)) /* PIO device data register */ +#define ATA_PIO_FED (*(REG32_PTR_T)(0x38E00058)) /* PIO device Feature/Error register */ +#define ATA_PIO_SCR (*(REG32_PTR_T)(0x38E0005C)) /* PIO sector count register */ +#define ATA_PIO_LLR (*(REG32_PTR_T)(0x38E00060)) /* PIO device LBA low register */ +#define ATA_PIO_LMR (*(REG32_PTR_T)(0x38E00064)) /* PIO device LBA middle register */ +#define ATA_PIO_LHR (*(REG32_PTR_T)(0x38E00068)) /* PIO device LBA high register */ +#define ATA_PIO_DVR (*(REG32_PTR_T)(0x38E0006C)) /* PIO device register */ +#define ATA_PIO_CSD (*(REG32_PTR_T)(0x38E00070)) /* PIO device command/status register */ +#define ATA_PIO_DAD (*(REG32_PTR_T)(0x38E00074)) /* PIO control/alternate status register */ +#define ATA_PIO_READY (*(REG32_PTR_T)(0x38E00078)) /* PIO data read/write ready */ +#define ATA_PIO_RDATA (*(REG32_PTR_T)(0x38E0007C)) /* PIO read data from device register */ +#define BUS_FIFO_STATUS (*(REG32_PTR_T)(0x38E00080)) /* Reserved */ +#define ATA_FIFO_STATUS (*(REG32_PTR_T)(0x38E00084)) /* Reserved */ + +/* 29. CHIP ID */ +#define REG_ONE (*(REG32_PTR_T)(0x3D100000)) /* Receive the first 32 bits from a fuse box */ +#define REG_TWO (*(REG32_PTR_T)(0x3D100004)) /* Receive the other 8 bits from a fuse box */ + diff --git a/firmware/export/system.h b/firmware/export/system.h index dc38532..2f6ceb3 100644 --- a/firmware/export/system.h +++ b/firmware/export/system.h @@ -35,6 +35,8 @@ struct flash_header { char version[32]; }; +void UIE(unsigned int pc, unsigned int num); + bool detect_flashed_romimage(void); bool detect_flashed_ramimage(void); bool detect_original_firmware(void); diff --git a/firmware/system.c b/firmware/system.c index 7163468..389ecea 100644 --- a/firmware/system.c +++ b/firmware/system.c @@ -233,12 +233,18 @@ static const char* const uiename[] = { "Divide by zero" }; +int bla(int arg) +{ + return arg+1; +} + /* Unexpected Interrupt or Exception handler. Currently only deals with exceptions, but will deal with interrupts later. */ void UIE(unsigned int pc, unsigned int num) __attribute__((noreturn)); void UIE(unsigned int pc, unsigned int num) { +#warning got here char str[32]; lcd_clear_display(); diff --git a/firmware/target/arm/s5l8700/ata-nand-s5l8700.c b/firmware/target/arm/s5l8700/ata-nand-s5l8700.c new file mode 100644 index 0000000..dd0ae7a --- /dev/null +++ b/firmware/target/arm/s5l8700/ata-nand-s5l8700.c @@ -0,0 +1,94 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id$ + * + * Copyright (C) 2007 Dave Chapman + * + * All files in this archive are subject to the GNU General Public License. + * See the file COPYING in the source tree root for full license agreement. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#include "ata.h" +#include "ata-target.h" +#include "ata_idle_notify.h" +#include "system.h" +#include <string.h> +#include "thread.h" +#include "led.h" +#include "disk.h" +#include "panic.h" +#include "usb.h" + +/* for compatibility */ +int ata_spinup_time = 0; + +long last_disk_activity = -1; + +/** static, private data **/ +static bool initialized = false; + +static long next_yield = 0; +#define MIN_YIELD_PERIOD 2000 + +/* API Functions */ + +void ata_led(bool onoff) +{ + led(onoff); +} + +int ata_read_sectors(IF_MV2(int drive,) unsigned long start, int incount, + void* inbuf) +{ + +} + +int ata_write_sectors(IF_MV2(int drive,) unsigned long start, int count, + const void* outbuf) +{ +} + +void ata_spindown(int seconds) +{ + (void)seconds; +} + +bool ata_disk_is_active(void) +{ + return 0; +} + +void ata_sleep(void) +{ +} + +void ata_spin(void) +{ +} + +/* Hardware reset protocol as specified in chapter 9.1, ATA spec draft v5 */ +int ata_hard_reset(void) +{ + return 0; +} + +int ata_soft_reset(void) +{ + return 0; +} + +void ata_enable(bool on) +{ +} + +int ata_init(void) +{ +} diff --git a/firmware/target/arm/s5l8700/boot.lds b/firmware/target/arm/s5l8700/boot.lds new file mode 100644 index 0000000..757abaa --- /dev/null +++ b/firmware/target/arm/s5l8700/boot.lds @@ -0,0 +1,54 @@ +#include "config.h" + +ENTRY(start) +OUTPUT_FORMAT(elf32-littlearm) +OUTPUT_ARCH(arm) +STARTUP(target/arm/s5l8700/crt0.o) + +/* DRAMORIG is in fact 0x8000000 but remapped to 0x0 */ +#define DRAMORIG 0x0 +#define DRAMSIZE 16M +# +#define IRAMORIG 0x22000000 +#define IRAMSIZE 256K + +/* This is not available in all versions of the S5L8700 */ +#define FLASHORIG 0x24000000 +#define FLASHSIZE 1M + +SECTIONS +{ + . = IRAMORIG; + + .text : { + *(.init.text) + *(.text*) + } + + .data : { + *(.icode) + *(.irodata) + *(.idata) + *(.data*) + *(.ncdata*); + _dataend = . ; + } + + .stack : + { + *(.stack) + _stackbegin = .; + stackbegin = .; + . += 0x2000; + _stackend = .; + stackend = .; + } + + .bss : { + _edata = .; + *(.bss*); + *(.ibss); + *(.ncbss*); + _end = .; + } +} diff --git a/firmware/target/arm/s5l8700/crt0.S b/firmware/target/arm/s5l8700/crt0.S new file mode 100644 index 0000000..3ecabde --- /dev/null +++ b/firmware/target/arm/s5l8700/crt0.S @@ -0,0 +1,117 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id$ + * + * Copyright (C) 2008 by Marcoen Hirschberg + * + * All files in this archive are subject to the GNU General Public License. + * See the file COPYING in the source tree root for full license agreement. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#include "config.h" +#include "cpu.h" + + .section .init.text,"ax",%progbits + + .global start +start: + /* Exception vectors */ + b newstart + b undef_instr_handler + b software_int_handler + b prefetch_abort_handler + b data_abort_handler + b reserved_handler + b irq_handler + b fiq_handler + .word 0x43554644 /* DFUC */ + +newstart: +#if 0 + msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */ + + /* Initialise bss section to zero */ + ldr r2, =_edata + ldr r3, =_end + mov r4, #0 +1: + cmp r3, r2 + strhi r4, [r2], #4 + bhi 1b + + /* Set up some stack and munge it with 0xdeadbeef */ + ldr sp, =stackend + ldr r2, =stackbegin + ldr r3, =0xdeadbeef +1: + cmp sp, r2 + strhi r3, [r2], #4 + bhi 1b + + /* Set up stack for IRQ mode */ + msr cpsr_c, #0xd2 + ldr sp, =irq_stack + + /* Set up stack for FIQ mode */ + msr cpsr_c, #0xd1 + ldr sp, =fiq_stack + + /* Let abort and undefined modes use IRQ stack */ + msr cpsr_c, #0xd7 + ldr sp, =irq_stack + msr cpsr_c, #0xdb + ldr sp, =irq_stack + + /* Switch back to supervisor mode */ + msr cpsr_c, #0xd3 +#endif + bl main + + + .text +/* .global UIE*/ + +/* All illegal exceptions call into UIE with exception address as first + * parameter. This is calculated differently depending on which exception + * we're in. Second parameter is exception number, used for a string lookup + * in UIE. */ +undef_instr_handler: + mov r0, lr + mov r1, #0 + b UIE + +/* We run supervisor mode most of the time, and should never see a software + * exception being thrown. Perhaps make it illegal and call UIE? */ +software_int_handler: +reserved_handler: + movs pc, lr + +prefetch_abort_handler: + sub r0, lr, #4 + mov r1, #1 + b UIE + +data_abort_handler: + sub r0, lr, #8 + mov r1, #2 + b UIE + +/* 256 words of IRQ stack */ + .space 256*4 +irq_stack: + +/* 256 words of FIQ stack */ + .space 256*4 +fiq_stack: + +end: + /*.word 0xA5A5A5A5 + .word 0x5A5A5A5A*/ diff --git a/firmware/target/arm/s5l8700/meizu-m6sl/adc-target.h b/firmware/target/arm/s5l8700/meizu-m6sl/adc-target.h new file mode 100644 index 0000000..c0a069a --- /dev/null +++ b/firmware/target/arm/s5l8700/meizu-m6sl/adc-target.h @@ -0,0 +1,33 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id$ + * + * Copyright (C) 2006 by Barry Wardell + * + * All files in this archive are subject to the GNU General Public License. + * See the file COPYING in the source tree root for full license agreement. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef _ADC_TARGET_H_ +#define _ADC_TARGET_H_ + +/* only two channels used by the Gigabeat */ +#define NUM_ADC_CHANNELS 1 + +#define ADC_UNKNOWN_1 0 +#define ADC_UNKNOWN_2 1 +#define ADC_BATTERY 2 +#define ADC_UNKNOWN_4 3 + +#define ADC_UNREG_POWER ADC_BATTERY /* For compatibility */ +#define ADC_READ_ERROR 0xFFFF + +#endif diff --git a/firmware/target/arm/s5l8700/meizu-m6sl/backlight-target.h b/firmware/target/arm/s5l8700/meizu-m6sl/backlight-target.h new file mode 100644 index 0000000..1dc334c --- /dev/null +++ b/firmware/target/arm/s5l8700/meizu-m6sl/backlight-target.h @@ -0,0 +1,27 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id$ + * + * Copyright (C) 2008 by Marcoen Hirschberg + * + * All files in this archive are subject to the GNU General Public License. + * See the file COPYING in the source tree root for full license agreement. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef BACKLIGHT_TARGET_H +#define BACKLIGHT_TARGET_H + +bool _backlight_init(void); +void _backlight_on(void); +void _backlight_off(void); +void _backlight_set_brightness(int brightness); + +#endif diff --git a/firmware/target/arm/s5l8700/meizu-m6sl/button-target.h b/firmware/target/arm/s5l8700/meizu-m6sl/button-target.h new file mode 100644 index 0000000..7d0d7a1 --- /dev/null +++ b/firmware/target/arm/s5l8700/meizu-m6sl/button-target.h @@ -0,0 +1,52 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id$ + * + * Copyright (C) 2006 by Linus Nielsen Feltzing + * + * All files in this archive are subject to the GNU General Public License. + * See the file COPYING in the source tree root for full license agreement. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef _BUTTON_TARGET_H_ +#define _BUTTON_TARGET_H_ + +#include <stdbool.h> +#include "config.h" + +#define HAS_BUTTON_HOLD + +bool button_hold(void); +void button_init_device(void); +int button_read_device(void); + +/* Toshiba Gigabeat specific button codes */ + +#define BUTTON_LEFT 0x00000001 +#define BUTTON_RIGHT 0x00000002 +#define BUTTON_UP 0x00000004 +#define BUTTON_DOWN 0x00000008 + +#define BUTTON_SELECT 0x00000010 + +#define BUTTON_MENU 0x00000020 +#define BUTTON_PLAY 0x00000040 + + +#define BUTTON_MAIN (BUTTON_MENU|BUTTON_LEFT|BUTTON_RIGHT\ + |BUTTON_UP|BUTTON_DOWN|BUTTON_SELECT|BUTTON_PLAY) + +#define BUTTON_REMOTE 0 + +#define POWEROFF_BUTTON BUTTON_PLAY +#define POWEROFF_COUNT 10 + +#endif /* _BUTTON_TARGET_H_ */ diff --git a/firmware/target/arm/s5l8700/meizu-m6sl/lcd-m6sl.c b/firmware/target/arm/s5l8700/meizu-m6sl/lcd-m6sl.c new file mode 100644 index 0000000..8e5a4f4 --- /dev/null +++ b/firmware/target/arm/s5l8700/meizu-m6sl/lcd-m6sl.c @@ -0,0 +1,133 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id$ + * + * Copyright (C) 2002 by Alan Korr + * + * All files in this archive are subject to the GNU General Public License. + * See the file COPYING in the source tree root for full license agreement. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#include "config.h" + +#include "hwcompat.h" +#include "kernel.h" +#include "lcd.h" +#include "system.h" +#include "cpu.h" + +/*** definitions ***/ + + +/** globals **/ + +static int xoffset; /* needed for flip */ + +/*** hardware configuration ***/ + +int lcd_default_contrast(void) +{ + return 0x1f; +} + +void lcd_set_contrast(int val) +{ +} + +void lcd_set_invert_display(bool yesno) +{ +} + +/* turn the display upside down (call lcd_update() afterwards) */ +void lcd_set_flip(bool yesno) +{ + /* TODO: flip mode isn't working. The commands in the else part of + this function are how the original firmware inits the LCD */ + + if (yesno) + { + xoffset = 132 - LCD_WIDTH; /* 132 colums minus the 128 we have */ + } + else + { + xoffset = 0; + } +} + + +/* LCD init */ +void lcd_init_device(void) +{ +} + +/*** Update functions ***/ + +/* Performance function that works with an external buffer + note that by and bheight are in 8-pixel units! */ +void lcd_blit_mono(const unsigned char *data, int x, int by, int width, + int bheight, int stride) +{ + /* Copy display bitmap to hardware */ + while (bheight--) + { + } +} + + +/* Performance function that works with an external buffer + note that by and bheight are in 8-pixel units! */ +void lcd_blit_grey_phase_blit(unsigned char *values, unsigned char *phases, + int x, int by, int width, int bheight, int stride) +{ + (void)values; + (void)phases; + (void)x; + (void)by; + (void)width; + (void)bheight; + (void)stride; +} + +/* Update the display. + This must be called after all other LCD functions that change the display. */ +void lcd_update(void) ICODE_ATTR; +void lcd_update(void) +{ + int y; + + /* Copy display bitmap to hardware */ + for (y = 0; y < LCD_FBHEIGHT; y++) + { + } +} + +/* Update a fraction of the display. */ +void lcd_update_rect(int, int, int, int) ICODE_ATTR; +void lcd_update_rect(int x, int y, int width, int height) +{ + int ymax; + + /* The Y coordinates have to work on even 8 pixel rows */ + ymax = (y + height-1) >> 3; + y >>= 3; + + if(x + width > LCD_WIDTH) + width = LCD_WIDTH - x; + if (width <= 0) + return; /* nothing left to do, 0 is harmful to lcd_write_data() */ + if(ymax >= LCD_FBHEIGHT) + ymax = LCD_FBHEIGHT-1; + + /* Copy specified rectange bitmap to hardware */ + for (; y <= ymax; y++) + { + } +} diff --git a/firmware/target/arm/s5l8700/system-s5l8700.c b/firmware/target/arm/s5l8700/system-s5l8700.c new file mode 100644 index 0000000..2d87cc8 --- /dev/null +++ b/firmware/target/arm/s5l8700/system-s5l8700.c @@ -0,0 +1,168 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id$ + * + * Copyright (C) 2007 by Rob Purchase + * + * All files in this archive are subject to the GNU General Public License. + * See the file COPYING in the source tree root for full license agreement. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ + +#include "kernel.h" +#include "system.h" +#include "panic.h" + +#define default_interrupt(name) \ + extern __attribute__((weak,alias("UIRQ"))) void name (void) + +void irq_handler(void) __attribute__((interrupt ("IRQ"), naked)); +void fiq_handler(void) __attribute__((interrupt ("FIQ"), naked)); + +default_interrupt(EXT0); +default_interrupt(EXT1); +default_interrupt(EXT2); +default_interrupt(EINT_VBUS); +default_interrupt(EINTG); +default_interrupt(INT_TIMERA); +default_interrupt(INT_WDT); +default_interrupt(INT_TIMERB); +default_interrupt(INT_TIMERC); +default_interrupt(INT_TIMERD); +default_interrupt(INT_DMA); +default_interrupt(INT_ALARM_RTC); +default_interrupt(INT_PRI_RTC); +default_interrupt(RESERVED1); +default_interrupt(INT_UART); +default_interrupt(INT_USB_HOST); +default_interrupt(INT_USB_FUNC); +default_interrupt(INT_LCDC_0); +default_interrupt(INT_LCDC_1); +default_interrupt(INT_ECC); +default_interrupt(INT_CALM); +default_interrupt(INT_ATA); +default_interrupt(INT_UART0); +default_interrupt(INT_SPDIF_OUT); +default_interrupt(INT_SDCI); +default_interrupt(INT_LCD); +default_interrupt(INT_SPI); +default_interrupt(INT_IIC); +default_interrupt(RESERVED2); +default_interrupt(INT_MSTICK); +default_interrupt(INT_ADC_WAKEUP); +default_interrupt(INT_ADC); + + + +static void (* const irqvector[])(void) = +{ + EXT0,EXT1,EXT2,EINT_VBUS,EINTG,INT_TIMERA,INT_WDT,INT_TIMERB, + INT_TIMERC,INT_TIMERD,INT_DMA,INT_ALARM_RTC,INT_PRI_RTC,RESERVED1,INT_UART,INT_USB_HOST, + INT_USB_FUNC,INT_LCDC_0,INT_LCDC_1,INT_ECC,INT_CALM,INT_ATA,INT_UART0,INT_SPDIF_OUT, + INT_SDCI,INT_LCD,INT_SPI,INT_IIC,RESERVED2,INT_MSTICK,INT_ADC_WAKEUP,INT_ADC +}; + +static const char * const irqname[] = +{ + "EXT0","EXT1","EXT2","EINT_VBUS","EINTG","INT_TIMERA","INT_WDT","INT_TIMERB", + "INT_TIMERC","INT_TIMERD","INT_DMA","INT_ALARM_RTC","INT_PRI_RTC","Reserved","INT_UART","INT_USB_HOST", + "INT_USB_FUNC","INT_LCDC_0","INT_LCDC_1","INT_ECC","INT_CALM","INT_ATA","INT_UART0","INT_SPDIF_OUT", + "INT_SDCI","INT_LCD","INT_SPI","INT_IIC","Reserved","INT_MSTICK","INT_ADC_WAKEUP","INT_ADC" +}; + +static void UIRQ(void) +{ + unsigned int offset = INTOFFSET; + panicf("Unhandled IRQ %02X: %s", offset, irqname[offset]); +} + +void irq_handler(void) +{ + /* + * Based on: linux/arch/arm/kernel/entry-armv.S and system-meg-fx.c + */ + + asm volatile( "stmfd sp!, {r0-r7, ip, lr} \n" /* Store context */ + "sub sp, sp, #8 \n"); /* Reserve stack */ + + int irq_no = INTOFFSET; /* Read clears the corresponding IRQ status */ + + if ((irq_no & (1<<31)) == 0) /* Ensure invalid flag is not set */ + { + irqvector[irq_no](); + } + + asm volatile( "add sp, sp, #8 \n" /* Cleanup stack */ + "ldmfd sp!, {r0-r7, ip, lr} \n" /* Restore context */ + "subs pc, lr, #4 \n"); /* Return from IRQ */ +} + +void fiq_handler(void) +{ + asm volatile ( + "subs pc, lr, #4 \r\n" + ); +} + + +static void gpio_init(void) +{ +} + +static void clock_init(void) +{ +} + + +void system_init(void) +{ +} + +void system_reboot(void) +{ +} + +int system_memory_guard(int newmode) +{ + (void)newmode; + return 0; +} + +#ifdef HAVE_ADJUSTABLE_CPU_FREQ + +void set_cpu_frequency(long frequency) +{ + if (cpu_frequency == frequency) + return; + + /* CPU/COP frequencies can be scaled between Fbus (min) and Fsys (max). + Fbus should not be set below ~32Mhz with LCD enabled or the display + will be garbled. */ + if (frequency == CPUFREQ_MAX) + { + } + else if (frequency == CPUFREQ_NORMAL) + { + } + else + { + } + + asm volatile ( + "nop \n\t" + "nop \n\t" + "nop \n\t" + ); + + cpu_frequency = frequency; +} + +#endif diff --git a/firmware/target/arm/s5l8700/system-target.h b/firmware/target/arm/s5l8700/system-target.h new file mode 100644 index 0000000..158bc44 --- /dev/null +++ b/firmware/target/arm/s5l8700/system-target.h @@ -0,0 +1,35 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id$ + * + * Copyright (C) 2007 by Dave Chapman + * + * All files in this archive are subject to the GNU General Public License. + * See the file COPYING in the source tree root for full license agreement. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef SYSTEM_TARGET_H +#define SYSTEM_TARGET_H + +#include "system-arm.h" + +#define CPUFREQ_DEFAULT 32000000 +#define CPUFREQ_NORMAL 48000000 +#define CPUFREQ_MAX 192000000 + +#define inl(a) (*(volatile unsigned long *) (a)) +#define outl(a,b) (*(volatile unsigned long *) (b) = (a)) +#define inb(a) (*(volatile unsigned char *) (a)) +#define outb(a,b) (*(volatile unsigned char *) (b) = (a)) +#define inw(a) (*(volatile unsigned short *) (a)) +#define outw(a,b) (*(volatile unsigned short *) (b) = (a)) + +#endif /* SYSTEM_TARGET_H */ diff --git a/tools/configure b/tools/configure index 3d9afdb..6410f90 100755 --- a/tools/configure +++ b/tools/configure @@ -248,6 +248,14 @@ arm9tdmicc () { gccchoice="4.0.3" } +arm940tbecc () { + prefixtools arm-elf- + GCCOPTS="$CCOPTS -mbig-endian -mcpu=arm940t -mlong-calls" + GCCOPTIMIZE="-fomit-frame-pointer" + endian="big" + gccchoice="4.0.3" +} + arm946cc () { prefixtools arm-elf- GCCOPTS="$CCOPTS -mcpu=arm9e -mlong-calls" @@ -676,12 +684,10 @@ cat <<EOF ==Tatung== ==Olympus== ==Logik== 60) Elio TPJ-1022 70) M:Robe 500 80) DAX 1GB MP3/DAB 71) M:Robe 100 - - ==Creative== ==Philips== - 90) Zen Vision:M 30GB 100) GoGear SA9200 + ==Creative== ==Philips== ==Meizu== + 90) Zen Vision:M 30GB 100) GoGear SA9200 110) M6SL 91) Zen Vision:M 60GB 101) GoGear HDD1630 92) Zen Vision - EOF buildfor=`input`; @@ -1720,6 +1726,27 @@ fi t_model="hdd1630" ;; + 110|meizum6sl) + target_id=20 + modelname="meizum6sl" + target="-DMEIZU_M6SL" + memory=16 # always + arm940tbecc + tool="cp" + bmp2rb_mono="$rootdir/tools/bmp2rb -f 0" + bmp2rb_native="$rootdir/tools/bmp2rb -f 4" + output="rockbox.meizu" + appextra="recorder:gui" + plugins="no" #FIXME + swcodec="yes" + toolset=$genericbitmaptools + boottool="cp" + bootoutput="rockboot.ebn" + # architecture, manufacturer and model for the target-tree build + t_cpu="arm" + t_manufacturer="s5l8700" + t_model="meizu-m6sl" + ;; *) echo "Please select a supported target platform!" exit diff --git a/tools/makesrc.inc b/tools/makesrc.inc index 846df8c..be9c34e 100644 --- a/tools/makesrc.inc +++ b/tools/makesrc.inc @@ -11,4 +11,5 @@ SRC := $(shell cat SOURCES | $(CC) -DMEMORYSIZE=$(MEMORYSIZE) $(INCLUDES) \ $(TARGET) $(DEFINES) $(EXTRA_DEFINES) -E -P -include "config.h" - 2>/dev/null \ -| grep -v "^\#") +| grep -v "^\#" | xargs ls) +#| grep -v "^\#") diff --git a/tools/rockboxdev.sh b/tools/rockboxdev.sh index fd4982b..77442c8 100755 --- a/tools/rockboxdev.sh +++ b/tools/rockboxdev.sh @@ -2,7 +2,7 @@ # this is where this script will store downloaded files and check for already # downloaded files -dlwhere="/tmp/rbdev-dl" +dlwhere="/usr/tmp/rbdev-dl" # will append the target string to the prefix dir mentioned here # Note that the user running this script must be able to do make install in @@ -12,7 +12,7 @@ prefix="/usr/local" # This directory is used to extract all files and to build everything in. It # must not exist before this script is invoked (as a security measure). -builddir="/tmp/rbdev-build" +builddir="/usr/tmp/rbdev-build" # This script needs to use GNU Make. On Linux systems, GNU Make is invoked # by running the "make" command, on most BSD systems, GNU Make is invoked diff --git a/uisimulator/sdl/button.c b/uisimulator/sdl/button.c index ba384b3..ee11174 100644 --- a/uisimulator/sdl/button.c +++ b/uisimulator/sdl/button.c @@ -802,6 +802,7 @@ void button_event(int key, bool pressed) case SDLK_KP_ENTER: new_btn = BUTTON_MENU; break; + #elif CONFIG_KEYPAD == CREATIVEZVM_PAD case SDLK_KP1: new_btn = BUTTON_BACK; @@ -886,6 +887,34 @@ void button_event(int key, bool pressed) break; case SDLK_s: new_btn = BUTTON_VOL_UP; + +#elif CONFIG_KEYPAD == MEIZU_M6SL_PAD + case SDLK_KP1: + new_btn = BUTTON_PREV; + break; + case SDLK_KP3: + new_btn = BUTTON_NEXT; + break; + case SDLK_KP_ENTER: + case SDLK_RETURN: + case SDLK_a: + new_btn = BUTTON_PLAY; + break; + case SDLK_KP_PERIOD: + case SDLK_INSERT: + new_btn = BUTTON_MENU; + break; + case SDLK_KP8: + case SDLK_UP: + new_btn = BUTTON_UP; + break; + case SDLK_KP2: + case SDLK_DOWN: + new_btn = BUTTON_DOWN; + break; + case SDLK_KP5: + case SDLK_SPACE: + new_btn = BUTTON_SELECT; break; #else #error No keymap defined! diff --git a/uisimulator/sdl/uisdl.h b/uisimulator/sdl/uisdl.h index abd320a..dde505b 100644 --- a/uisimulator/sdl/uisdl.h +++ b/uisimulator/sdl/uisdl.h @@ -404,6 +404,19 @@ #define UI_LCD_FGCOLOR 0, 0, 0 /* foreground color of LCD (no backlight) */ #define UI_LCD_FGCOLORLIGHT 0, 0, 0 /* foreground color of LCD (backlight) */ +#elif defined(MEIZU_M6SL) +#define UI_TITLE "Meizu M6" +#define UI_WIDTH 512 /* width of GUI window */ +#define UI_HEIGHT 322 /* height of GUI window */ +#define UI_LCD_POSX 39 /* x position of lcd */ +#define UI_LCD_POSY 38 /* y position of lcd */ +#define UI_LCD_WIDTH 320 +#define UI_LCD_HEIGHT 240 +#define UI_LCD_BGCOLOR 32, 32, 32 /* bkgnd color of LCD (no backlight) */ +#define UI_LCD_BGCOLORLIGHT 192, 192, 192 /* bkgnd color of LCD (backlight) */ +#define UI_LCD_FGCOLOR 0, 0, 0 /* foreground color of LCD (no backlight) */ +#define UI_LCD_FGCOLORLIGHT 0, 0, 0 /* foreground color of LCD (backlight) */ + #endif extern SDL_Surface *gui_surface; extern bool background; /* True if the background image is enabled */ |