More PP502x clock setup rework. This should fix the freezes on PP5020 once and for all. Enabled clock scaling for H10. * CPUFREQ_MAX changed to 78MHz * To be cleaned up soon.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13767 a1c6a512-1295-4272-9138-f99709370657

6 files changed, 34 insertions, 15 deletions

diff --git a/apps/debug_menu.c b/apps/debug_menu.c
index 086ca9e..eec0dc3 100644
--- a/apps/debug_menu.c
+++ b/apps/debug_menu.c
@@ -1082,7 +1082,6 @@ bool dbg_ports(void)
         lcd_puts(0, line++, buf);
         snprintf(buf, sizeof(buf), "GPIO_C: %02x GPIO_I: %02x", gpio_c, gpio_i);
         lcd_puts(0, line++, buf);
-        line++;
 
         gpio_d = GPIOD_INPUT_VAL;
         gpio_e = GPIOE_INPUT_VAL;
@@ -1102,11 +1101,15 @@ bool dbg_ports(void)
         
         snprintf(buf, sizeof(buf), "CLOCK_SRC:   %08lx", inl(0x60006020));
         lcd_puts(0, line++, buf);
+        snprintf(buf, sizeof(buf), "CLOCK_0x2C:  %08lx", inl(0x6000602c));
+        lcd_puts(0, line++, buf);
+        snprintf(buf, sizeof(buf), "CLOCK_0xA0:  %08lx", inl(0x600060a0));
+        lcd_puts(0, line++, buf);
         snprintf(buf, sizeof(buf), "PLL_CONTROL: %08lx", inl(0x60006034));
         lcd_puts(0, line++, buf);
         snprintf(buf, sizeof(buf), "PLL_STATUS:  %08lx", inl(0x6000603c));
         lcd_puts(0, line++, buf);
-        snprintf(buf, sizeof(buf), "DEV_PLL:     %08lx", inl(0x70000020));
+        snprintf(buf, sizeof(buf), "DEV_0x34:    %08lx", inl(0x70000034));
         lcd_puts(0, line++, buf);
 
 #if defined(IRIVER_H10) || defined(IRIVER_H10_5GB)
diff --git a/firmware/export/config-h10.h b/firmware/export/config-h10.h
index b0617eb..7a97f4c 100644
--- a/firmware/export/config-h10.h
+++ b/firmware/export/config-h10.h
@@ -156,7 +156,7 @@
 #define CONFIG_LED LED_VIRTUAL
 
 /* Define this if you have adjustable CPU frequency */
-/*#define HAVE_ADJUSTABLE_CPU_FREQ*/
+#define HAVE_ADJUSTABLE_CPU_FREQ
 
 #define MI4_FORMAT
 #define BOOTFILE_EXT    "mi4"
diff --git a/firmware/export/config-h10_5gb.h b/firmware/export/config-h10_5gb.h
index 37a1a47..add682c 100644
--- a/firmware/export/config-h10_5gb.h
+++ b/firmware/export/config-h10_5gb.h
@@ -139,7 +139,7 @@
 #define CONFIG_LED LED_VIRTUAL
 
 /* Define this if you have adjustable CPU frequency */
-/*#define HAVE_ADJUSTABLE_CPU_FREQ*/
+#define HAVE_ADJUSTABLE_CPU_FREQ
 
 #define MI4_FORMAT
 #define BOOTFILE_EXT    "mi4"
diff --git a/firmware/export/pp5020.h b/firmware/export/pp5020.h
index 7475cc7..f35b4c4 100644
--- a/firmware/export/pp5020.h
+++ b/firmware/export/pp5020.h
@@ -131,6 +131,11 @@
 #define DEV_IDE0        0x2000000
 #define DEV_LCD         0x4000000
 
+/* clock control */
+#define CLOCK_SOURCE    (*(volatile unsigned long *)(0x60006020))
+#define PLL_CONTROL     (*(volatile unsigned long *)(0x60006034))
+#define PLL_STATUS      (*(volatile unsigned long *)(0x6000603c))
+
 /* Processors Control */
 #define CPU_CTL          (*(volatile unsigned long *)(0x60007000))
 #define COP_CTL          (*(volatile unsigned long *)(0x60007004))
diff --git a/firmware/target/arm/system-arm.h b/firmware/target/arm/system-arm.h
index 26b8ac3..99cab9e 100644
--- a/firmware/target/arm/system-arm.h
+++ b/firmware/target/arm/system-arm.h
@@ -31,12 +31,12 @@
 #if CONFIG_CPU != S3C2440 && CONFIG_CPU != PNX0101
 
 /* TODO: Finish targeting this stuff */
-#define CPUFREQ_DEFAULT_MULT 8
+#define CPUFREQ_DEFAULT_MULT 4
 #define CPUFREQ_DEFAULT 24000000
-#define CPUFREQ_NORMAL_MULT 10
+#define CPUFREQ_NORMAL_MULT 5
 #define CPUFREQ_NORMAL 30000000
-#define CPUFREQ_MAX_MULT 25
-#define CPUFREQ_MAX 75000000
+#define CPUFREQ_MAX_MULT 13
+#define CPUFREQ_MAX 78000000
 
 #endif
 
diff --git a/firmware/target/arm/system-pp502x.c b/firmware/target/arm/system-pp502x.c
index 658ea0e..4542913 100644
--- a/firmware/target/arm/system-pp502x.c
+++ b/firmware/target/arm/system-pp502x.c
@@ -152,6 +152,7 @@ static void ipod_init_cache(void)
 void set_cpu_frequency(long frequency)
 {
     unsigned long postmult, pll_control;
+    unsigned long unknown1, unknown2;
 
 # if NUM_CORES > 1
     /* Using mutex or spinlock isn't safe here. */
@@ -166,17 +167,25 @@ void set_cpu_frequency(long frequency)
         postmult = CPUFREQ_DEFAULT_MULT;
     cpu_frequency = frequency;
 
-    /* Enable PLL? */
-    outl(inl(0x70000020) | (1<<30), 0x70000020);
+    unknown2 = inl(0x600060a0);
 
-    /* Select 24MHz crystal as clock source? */
+    outl(inl(0x70000020) | (1<<30), 0x70000020);   /* Enable PLL power */
+
+    /* Set clock source #1 to 24MHz and select it */
     outl((inl(0x60006020) & 0x0ffffff0) | 0x10000002, 0x60006020);
+    
+    outl(unknown2 & 0x3fffffff, 0x600060a0);
+    
+    unknown1 = (138 * postmult + 255) >> 8;
+    if (unknown1 > 15)
+        unknown1 = 15;
+    outl((unknown1 << 8) | unknown1, 0x70000034);
 
-    /* Clock frequency = (24/8)*postmult */
-    pll_control = 0x8a020000 | 8 | (postmult << 8);
+    /* PLL frequency = (24/4)*postmult */
+    pll_control = 0x8a020000 | 4 | (postmult << 8);
     outl(pll_control, 0x60006034);
 # if CONFIG_CPU == PP5020
-    outl(0xd198, 0x6000603c);     /* magic sequence */
+    outl(0xd19b, 0x6000603c);     /* magic sequence */
     outl(pll_control, 0x60006034);
     udelay(500);                  /* wait for relock */
 # else /* PP5022, PP5024 */
@@ -186,6 +195,8 @@ void set_cpu_frequency(long frequency)
     /* Select PLL as clock source? */
     outl((inl(0x60006020) & 0x0fffff0f) | 0x20000070, 0x60006020);
     
+    outl(unknown2, 0x600060a0);
+    
 # if NUM_CORES > 1
     boostctrl_mtx.locked = 0;
 # endif
@@ -199,7 +210,7 @@ void ipod_set_cpu_frequency(void)
     outl(inl(0x70000020) | (1<<30), 0x70000020);
 
     /* Select 24MHz crystal as clock source? */
-    outl((inl(0x60006020) & 0x0fffff0f) | 0x20000020, 0x60006020);
+    outl((inl(0x60006020) & 0x0ffffff0) | 0x10000002, 0x60006020);
 
     /* Clock frequency = (24/8)*25 = 75MHz */
     outl(0x8a020000 | 8 | (25 << 8), 0x60006034);