Cache functions should include data and instruction barriers.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17150 a1c6a512-1295-4272-9138-f99709370657

2 files changed, 18 insertions, 7 deletions

diff --git a/firmware/target/arm/imx31/gigabeat-s/system-target.h b/firmware/target/arm/imx31/gigabeat-s/system-target.h
index 17f1593..e48b5d1 100644
--- a/firmware/target/arm/imx31/gigabeat-s/system-target.h
+++ b/firmware/target/arm/imx31/gigabeat-s/system-target.h
@@ -42,8 +42,13 @@ static inline void invalidate_icache(void)
     asm volatile(
         /* Clean and invalidate entire data cache */
         "mcr p15, 0, %0, c7, c14, 0 \n"
-        /* Invalidate entire instruction cache */
+        /* Invalidate entire intruction cache
+         * Also flushes the branch target cache */
         "mcr p15, 0, %0, c7, c5, 0  \n"
+        /* Data synchronization barrier */
+        "mcr p15, 0, %0, c7, c10, 4 \n"
+        /* Flush prefetch buffer */
+        "mcr p15, 0, %0, c7, c5, 4  \n"
         : : "r"(0)
     );
 }
@@ -54,6 +59,8 @@ static inline void flush_icache(void)
     asm volatile (
         /* Clean entire data cache */
         "mcr p15, 0, %0, c7, c10, 0 \n"
+        /* Data synchronization barrier */
+        "mcr p15, 0, r2, c7, c10, 4 \n"
         : : "r"(0)
     );
 }
diff --git a/firmware/target/arm/mmu-arm.c b/firmware/target/arm/mmu-arm.c
index 5fa05d1..ffca7a4 100644
--- a/firmware/target/arm/mmu-arm.c
+++ b/firmware/target/arm/mmu-arm.c
@@ -90,9 +90,11 @@ void enable_mmu(void) {
 void __attribute__((naked)) invalidate_dcache_range(const void *base, unsigned int size)
 {
     asm volatile(
-        "add    r1, r1, r0          \n"
-        "mcrr   p15, 0, r1, r0, c14 \n"
-        "bx     lr                  \n"
+        "add    r1, r1, r0             \n"
+        "mov    r2, #0                 \n"
+        "mcrr   p15, 0, r1, r0, c14    \n" /* Clean and invalidate dcache range */
+        "mcr    p15, 0, r2, c7, c10, 4 \n" /* Data synchronization barrier */
+        "bx     lr                     \n"
     );
     (void)base; (void)size;
 }
@@ -140,9 +142,11 @@ void invalidate_dcache_range(const void *base, unsigned int size) {
 void __attribute__((naked)) clean_dcache_range(const void *base, unsigned int size)
 {
     asm volatile(
-        "add    r1, r1, r0          \n"
-        "mcrr   p15, 0, r1, r0, c12 \n"
-        "bx     lr                  \n"
+        "add    r1, r1, r0             \n"
+        "mov    r2, #0                 \n"
+        "mcrr   p15, 0, r1, r0, c12    \n" /* Clean dcache range */
+        "mcr    p15, 0, r2, c7, c10, 4 \n" /* Data synchronization barrier */
+        "bx     lr                     \n"
     );
     (void)base; (void)size;
 }