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authorJean-Philippe Bernardy <jeanphilippe.bernardy@gmail.com>2005-02-15 14:00:21 +0000
committerJean-Philippe Bernardy <jeanphilippe.bernardy@gmail.com>2005-02-15 14:00:21 +0000
commita11bb63d1ed4715fad571cb388cc2b104edc52bb (patch)
tree3c36cc67383d13e4c28628f16fd6c6aa7ad4f11d
parenteffb196053664f60b465db5ca0bb0c06b02b6eae (diff)
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better PLL support & slight fix (probably in keepalive handling)
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@5951 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r--firmware/export/system.h3
-rw-r--r--firmware/system.c47
2 files changed, 40 insertions, 10 deletions
diff --git a/firmware/export/system.h b/firmware/export/system.h
index 60febf3..f9da0d2 100644
--- a/firmware/export/system.h
+++ b/firmware/export/system.h
@@ -190,6 +190,9 @@ static inline void invalidate_icache(void)
#elif CONFIG_CPU == TCC730
+extern void set_pll_freq(int pll_index, long freq_out);
+
+
extern void* volatile interrupt_vector[16] __attribute__ ((section(".idata")));
extern void ddma_transfer(int dir, int mem, long intAddr, long extAddr,
diff --git a/firmware/system.c b/firmware/system.c
index 693c4a1..eb6c6ee 100644
--- a/firmware/system.c
+++ b/firmware/system.c
@@ -85,25 +85,51 @@ extern int icodecopy;
extern int icodesize;
extern int icodestart;
+/* change the CPU frequency */
+void set_pll_freq(int pll_index, long freq_out) {
+ volatile unsigned int* plldata;
+ volatile unsigned char* pllcon;
+ if (pll_index == 0) {
+ plldata = &PLL0DATA;
+ pllcon = &PLL0CON;
+ } else {
+ plldata = &PLL1DATA;
+ pllcon = &PLL1CON;
+ }
+ /* VC0 is 32768 Hz */
+#define VC0FREQ (32768L)
+ unsigned m = (freq_out / VC0FREQ) - 2;
+ /* TODO: if m is too small here, use the divider bits [0,1] */
+ *plldata = m << 2;
+ *pllcon |= 0x1; /* activate */
+ do {
+ } while ((*pllcon & 0x2) == 0); /* wait for stabilization */
+}
+
/* called by crt0 */
void system_init(void)
{
/* Disable watchdog */
WDTEN = 0xA5;
+
+ /****************
+ * GPIO ports
+ */
+
+ /* keep alive (?) -- clear the bit to prevent crash at start (??) */
+ P8 = 0x00;
+ P8CON = 0x01;
- /* Setup the CPU */
+ /********
+ * CPU
+ */
/* PLL0 (cpu osc. frequency) */
#if 0
- PLL0DATA = 0xf98;
- PLL0CON = 0x1; /* activate */
- do {
- asm "nop";
- } while ((PLL0CON & 0x2) == 0); /* wait for stabilization */
-
- PLL0CON = 0x5; /* use as CPU clock */
+ set_pll_freq(0, CPU_FREQ);
+ PLL0CON |= 0x4; /* use as CPU clock */
#endif
@@ -118,11 +144,12 @@ void system_init(void)
/***************************
- * Interrupt mask
+ * Interrupts
*/
- /* interrupt priorities ? */
+ /* priorities ? */
+ /* mask */
IMR0 = 0;
IMR1 = 0;