diff options
| author | Jens Arnold <amiconn@rockbox.org> | 2007-11-08 06:52:48 +0000 |
|---|---|---|
| committer | Jens Arnold <amiconn@rockbox.org> | 2007-11-08 06:52:48 +0000 |
| commit | a50a80e1a3bcff9e3c739d796605c10e1f8e8d05 (patch) | |
| tree | af615b3db3d9561bb8509feaf77fce68dc902f7c | |
| parent | 57d71e4267ecf66c84173f8ff3606091187b93b1 (diff) | |
| download | rockbox-a50a80e1a3bcff9e3c739d796605c10e1f8e8d05.zip rockbox-a50a80e1a3bcff9e3c739d796605c10e1f8e8d05.tar.gz rockbox-a50a80e1a3bcff9e3c739d796605c10e1f8e8d05.tar.bz2 rockbox-a50a80e1a3bcff9e3c739d796605c10e1f8e8d05.tar.xz | |
Mini 2nd Gen: Almost doubled LCD update speed when not boosted (68.5->129fps @30MHz) by handling the serial LCD clock divider.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@15524 a1c6a512-1295-4272-9138-f99709370657
| -rw-r--r-- | firmware/export/pp5020.h | 2 | ||||
| -rw-r--r-- | firmware/target/arm/system-pp502x.c | 9 |
2 files changed, 11 insertions, 0 deletions
diff --git a/firmware/export/pp5020.h b/firmware/export/pp5020.h index 47f73b9..b559aa3 100644 --- a/firmware/export/pp5020.h +++ b/firmware/export/pp5020.h @@ -147,6 +147,8 @@ /* clock control */ #define CLOCK_SOURCE (*(volatile unsigned long *)(0x60006020)) +#define MLCD_SCLK_DIV (*(volatile unsigned long *)(0x6000602c)) + /* bits 0..1: Mono LCD bridge serial clock divider: 1 / (n+1) */ #define PLL_CONTROL (*(volatile unsigned long *)(0x60006034)) #define PLL_STATUS (*(volatile unsigned long *)(0x6000603c)) #define ADC_CLOCK_SRC (*(volatile unsigned long *)(0x60006094)) diff --git a/firmware/target/arm/system-pp502x.c b/firmware/target/arm/system-pp502x.c index 0f24997..a1c4d16 100644 --- a/firmware/target/arm/system-pp502x.c +++ b/firmware/target/arm/system-pp502x.c @@ -178,6 +178,9 @@ static void pp_set_cpu_frequency(long frequency) case CPUFREQ_MAX: CLOCK_SOURCE = 0x10007772; /* source #1: 24MHz, #2, #3, #4: PLL */ DEV_TIMING1 = 0x00000303; +#ifdef IPOD_MINI2G + MLCD_SCLK_DIV = 0x00000001; /* Mono LCD bridge serial clock divider */ +#endif #if CONFIG_CPU == PP5020 PLL_CONTROL = 0x8a020a03; /* 10/3 * 24MHz */ PLL_STATUS = 0xd19b; /* unlock frequencies > 66MHz */ @@ -196,6 +199,9 @@ static void pp_set_cpu_frequency(long frequency) case CPUFREQ_NORMAL: CLOCK_SOURCE = 0x10007772; /* source #1: 24MHz, #2, #3, #4: PLL */ DEV_TIMING1 = 0x00000303; +#ifdef IPOD_MINI2G + MLCD_SCLK_DIV = 0x00000000; /* Mono LCD bridge serial clock divider */ +#endif #if CONFIG_CPU == PP5020 PLL_CONTROL = 0x8a020504; /* 5/4 * 24MHz */ scale_suspend_core(false); @@ -220,6 +226,9 @@ static void pp_set_cpu_frequency(long frequency) default: CLOCK_SOURCE = 0x10002222; /* source #1, #2, #3, #4: 24MHz */ DEV_TIMING1 = 0x00000303; +#ifdef IPOD_MINI2G + MLCD_SCLK_DIV = 0x00000000; /* Mono LCD bridge serial clock divider */ +#endif PLL_CONTROL &= ~0x80000000; /* disable PLL */ cpu_frequency = CPUFREQ_DEFAULT; PROC_CTL(CURRENT_CORE) = 0x4800001f; nop; |