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| author | Jack Halpin <jack.halpin@gmail.com> | 2009-05-29 06:43:37 +0000 |
|---|---|---|
| committer | Jack Halpin <jack.halpin@gmail.com> | 2009-05-29 06:43:37 +0000 |
| commit | b714ace1634cd6da7f21fca10ac2e8981da7fc88 (patch) | |
| tree | 84226c4b9d07b2afeb75f57f755e6b3301fb5f66 | |
| parent | b4b7c7501e61b0c89233d8a43c8557053b859ddf (diff) | |
| download | rockbox-b714ace1634cd6da7f21fca10ac2e8981da7fc88.zip rockbox-b714ace1634cd6da7f21fca10ac2e8981da7fc88.tar.gz rockbox-b714ace1634cd6da7f21fca10ac2e8981da7fc88.tar.bz2 rockbox-b714ace1634cd6da7f21fca10ac2e8981da7fc88.tar.xz | |
AMSSansa: clock-target.h and debug-as3525 now use AS3525_FCLK_PREDIV correctly. Default frequency scheme remains 248/62/62.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21125 a1c6a512-1295-4272-9138-f99709370657
| -rw-r--r-- | firmware/target/arm/as3525/clock-target.h | 4 | ||||
| -rw-r--r-- | firmware/target/arm/as3525/debug-as3525.c | 11 |
2 files changed, 7 insertions, 8 deletions
diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h index c9b2ceb..923f4e7 100644 --- a/firmware/target/arm/as3525/clock-target.h +++ b/firmware/target/arm/as3525/clock-target.h @@ -89,8 +89,8 @@ /* FCLK */ #define AS3525_FCLK_SEL AS3525_CLK_PLLA -#define AS3525_FCLK_PREDIV 0 /* div = (8-n)/8 acts strange when used!*/ -#define AS3525_FCLK_POSTDIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_FCLK_FREQ) - 1) /*div=1/(n+1)*/ +#define AS3525_FCLK_PREDIV 0 /* div = (8-n)/8 Enter manually & postdiv will be calculated*/ +#define AS3525_FCLK_POSTDIV (CLK_DIV((AS3525_PLLA_FREQ*(8-AS3525_FCLK_PREDIV)/8), AS3525_FCLK_FREQ) - 1) /*div=1/(n+1)*/ /* PCLK */ #ifdef ASYNCHRONOUS_BUS diff --git a/firmware/target/arm/as3525/debug-as3525.c b/firmware/target/arm/as3525/debug-as3525.c index 8bd2ee1..7585f76 100644 --- a/firmware/target/arm/as3525/debug-as3525.c +++ b/firmware/target/arm/as3525/debug-as3525.c @@ -84,6 +84,8 @@ static unsigned read_cp15 (void) int calc_freq(int clk) { int out_div; + unsigned int prediv = ((unsigned int)CGU_PROC>>2) & 0x3; + unsigned int postdiv = ((unsigned int)CGU_PROC>>4) & 0xf; switch(clk) { /* clk_main = clk_int = 24MHz oscillator */ @@ -119,14 +121,11 @@ int calc_freq(int clk) case CLK_FCLK: switch(CGU_PROC & 3) { case 0: - return CLK_MAIN/ - ((8/(8-((CGU_PROC>>2)& 0x3)))*(((CGU_PROC>>4)& 0xf) + 1)); + return (CLK_MAIN * (8 - prediv)) / (8*(postdiv + 1)); case 1: - return calc_freq(CLK_PLLA)/ - ((8/(8-((CGU_PROC>>2)& 0x3)))*(((CGU_PROC>>4)& 0xf) + 1)); + return (calc_freq(CLK_PLLA) * (8 - prediv)) / (8*(postdiv + 1)); case 2: - return calc_freq(CLK_PLLB)/ - ((8/(8-((CGU_PROC>>2)& 0x3)))*(((CGU_PROC>>4)& 0xf) + 1)); + return (calc_freq(CLK_PLLB) * (8 - prediv)) / (8*(postdiv + 1)); default: return 0; } |