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authorJens Arnold <amiconn@rockbox.org>2007-07-07 05:58:29 +0000
committerJens Arnold <amiconn@rockbox.org>2007-07-07 05:58:29 +0000
commitc6437185b7a5331d7d36a440ad67d3c7cd3502f4 (patch)
treecf1158b698802ca66432819b5dda9d88a893669f
parent68f975be8524e89fe582b20f3231f161b6f85e26 (diff)
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Stop the crashes on some PP5022C targets (iPod Video, perhaps also Nano) introduced by the recent clock setup changes. Looks like some revisions of the chip don't reset the PLL_locked bit immediately after PLL setup.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13810 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r--firmware/target/arm/system-pp502x.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/firmware/target/arm/system-pp502x.c b/firmware/target/arm/system-pp502x.c
index 4542913..4fca846 100644
--- a/firmware/target/arm/system-pp502x.c
+++ b/firmware/target/arm/system-pp502x.c
@@ -175,7 +175,7 @@ void set_cpu_frequency(long frequency)
outl((inl(0x60006020) & 0x0ffffff0) | 0x10000002, 0x60006020);
outl(unknown2 & 0x3fffffff, 0x600060a0);
-
+
unknown1 = (138 * postmult + 255) >> 8;
if (unknown1 > 15)
unknown1 = 15;
@@ -189,9 +189,10 @@ void set_cpu_frequency(long frequency)
outl(pll_control, 0x60006034);
udelay(500); /* wait for relock */
# else /* PP5022, PP5024 */
+ udelay(250);
while (!(inl(0x6000603c) & 0x80000000)); /* wait for relock */
# endif
-
+
/* Select PLL as clock source? */
outl((inl(0x60006020) & 0x0fffff0f) | 0x20000070, 0x60006020);