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| author | Marcoen Hirschberg <marcoen@gmail.com> | 2007-01-17 18:15:50 +0000 |
|---|---|---|
| committer | Marcoen Hirschberg <marcoen@gmail.com> | 2007-01-17 18:15:50 +0000 |
| commit | c64684887ab49749326e2bab61df431a35ed7272 (patch) | |
| tree | a0b00e5de218523a389195dc994222d4575ebe20 | |
| parent | 020dbcd1cf035cf6978db155b8a746732bcc44b3 (diff) | |
| download | rockbox-c64684887ab49749326e2bab61df431a35ed7272.zip rockbox-c64684887ab49749326e2bab61df431a35ed7272.tar.gz rockbox-c64684887ab49749326e2bab61df431a35ed7272.tar.bz2 rockbox-c64684887ab49749326e2bab61df431a35ed7272.tar.xz | |
re-enable CPU scaling (between 100 and 300MHz again) with a new implementation
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@12047 a1c6a512-1295-4272-9138-f99709370657
| -rw-r--r-- | firmware/export/config-gigabeat.h | 3 | ||||
| -rw-r--r-- | firmware/target/arm/gigabeat/meg-fx/system-meg-fx.c | 18 |
2 files changed, 9 insertions, 12 deletions
diff --git a/firmware/export/config-gigabeat.h b/firmware/export/config-gigabeat.h index 9f02405..6e22e8d 100644 --- a/firmware/export/config-gigabeat.h +++ b/firmware/export/config-gigabeat.h @@ -126,8 +126,7 @@ #define HAVE_HEADPHONE_DETECTION /* Define this if you have adjustable CPU frequency */ -/* Not ready for prime-time */ -/* #define HAVE_ADJUSTABLE_CPU_FREQ */ +#define HAVE_ADJUSTABLE_CPU_FREQ #define BOOTFILE_EXT "gigabeat" #define BOOTFILE "rockbox." BOOTFILE_EXT diff --git a/firmware/target/arm/gigabeat/meg-fx/system-meg-fx.c b/firmware/target/arm/gigabeat/meg-fx/system-meg-fx.c index ca73b38..b7e59e6 100644 --- a/firmware/target/arm/gigabeat/meg-fx/system-meg-fx.c +++ b/firmware/target/arm/gigabeat/meg-fx/system-meg-fx.c @@ -75,22 +75,20 @@ void set_cpu_frequency(long frequency) { if (frequency == CPUFREQ_MAX) { - /* FCLK: 300MHz, HCLK: 100MHz, PCLK: 50MHz */ - /* MDIV: 97, PDIV: 1, SDIV: 2 */ - /* HDIV: 3, PDIV: 1 */ + asm volatile("mov r0, #0\n" + "mrc p15, 0, r0, c1, c0, 0\n" + "orr r0, r0, #3<<30\n" /* set to Asynchronous mode*/ + "mcr p15, 0, r0, c1, c0, 0" : : : "r0"); - MPLLCON = (97 << 12) | (1 << 4) | 2; - CLKDIVN = (3 << 1) | 1; FREQ = CPUFREQ_MAX; } else { - /* FCLK: 200MHz, HCLK: 100MHz, PCLK: 50MHz */ - /* MDIV: 62, PDIV: 1, SDIV: 2 */ - /* HDIV: 1, PDIV: 1 */ + asm volatile("mov r0, #0\n" + "mrc p15, 0, r0, c1, c0, 0\n" + "bic r0, r0, #3<<30\n" /* set to FastBus mode*/ + "mcr p15, 0, r0, c1, c0, 0" : : : "r0"); - MPLLCON = (62 << 12) | (1 << 4) | 2; - CLKDIVN = (1 << 1) | 1; FREQ = CPUFREQ_NORMAL; } } |