s5l870x : use mmu-arm.S

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25634 a1c6a512-1295-4272-9138-f99709370657

6 files changed, 31 insertions, 151 deletions

diff --git a/firmware/SOURCES b/firmware/SOURCES
index 95131ab..ac3adac 100644
--- a/firmware/SOURCES
+++ b/firmware/SOURCES
@@ -1369,7 +1369,7 @@ target/arm/tcc780x/cowond2/audio-cowond2.c
 
 #ifdef CPU_S5L870X
 target/arm/s5l8700/system-s5l8700.c
-target/arm/s5l8700/mmu-s5l8700.S
+target/arm/mmu-arm.S
 #ifndef SIMULATOR
 #ifndef BOOTLOADER
 target/arm/s5l8700/timer-s5l8700.c
diff --git a/firmware/export/as3525.h b/firmware/export/as3525.h
index 4a9ab5f..358b0c4 100644
--- a/firmware/export/as3525.h
+++ b/firmware/export/as3525.h
@@ -20,6 +20,8 @@
 #ifndef __AS3525_H__
 #define __AS3525_H__
 
+#define CACHEALIGN_BITS (5)
+
 #define UART_CHANNELS 1
 
 
diff --git a/firmware/export/s3c2440.h b/firmware/export/s3c2440.h
index da2ea89..d2de6d2 100644
--- a/firmware/export/s3c2440.h
+++ b/firmware/export/s3c2440.h
@@ -21,6 +21,8 @@
 #ifndef __S3C2440_H__
 #define __S3C2440_H__
 
+#define CACHEALIGN_BITS (5)
+
 #define LCD_BUFFER_SIZE (320*240*2)
 #define TTB_SIZE (0x4000)
 /* must be 16Kb (0x4000) aligned */
diff --git a/firmware/target/arm/mmu-arm.S b/firmware/target/arm/mmu-arm.S
index 947e96b..0119b26 100644
--- a/firmware/target/arm/mmu-arm.S
+++ b/firmware/target/arm/mmu-arm.S
@@ -22,7 +22,6 @@
 #include "cpu.h"
 
 /* Used by ARMv4 & ARMv5 CPUs with cp15 register and MMU */
-/* WARNING : assume size of a data cache line == 32 bytes */
 
 #if CONFIG_CPU == TCC7801 || CONFIG_CPU == AT91SAM9260
 /* MMU present but unused */
@@ -40,19 +39,38 @@
 #define USE_MMU
 #define CACHE_SIZE 16
 
+#elif CONFIG_CPU == S5L8701
+/* MMU not present */
+#define CACHE_SIZE 4
+
 #else
 #error Cache settings unknown for this CPU !
 
 #endif /* CPU specific configuration */
 
 @ Index format: 31:26 = index, N:5 = segment, remainder = SBZ
-@ assume 64-way set associative separate I/D caches, 32B (2^5) cache line size
+@ assume 64-way set associative separate I/D caches
 @ CACHE_SIZE = N (kB) = N*2^10 B
-@ number of lines = N*2^(10-5) = N*2^(5)
+@ number of lines = N*2^(10-CACHEALIGN_BITS)
 @ Index bits = 6
-@ Segment loops = N*2^(5-6) = N*2^(-1) = N/2
+@ Segment loops = N*2^(10-CACHEALIGN_BITS-6) = N*2^(4-CACHEALIGN_BITS)
+@ Segment loops = N/2^(CACHEALIGN_BITS - 4)
+@ Segment loops = N/(1<<(CACHEALIGN_BITS - 4))
+
+#ifdef CACHE_SIZE
 
+#if CACHEALIGN_BITS == 4
+#define INDEX_STEPS CACHE_SIZE
+#elif CACHEALIGN_BITS == 5
 #define INDEX_STEPS (CACHE_SIZE/2)
+#endif /* CACHEALIGN_BITS */
+
+@ assume 64-way set associative separate I/D caches (log2(64) == 6)
+@ Index format: 31:26 = index, M:N = segment, remainder = SBZ
+@ Segment bits = log2(cache size in bytes / cache line size in byte) - Index bits (== 6)
+@ N = CACHEALIGN_BITS
+
+#endif /* CACHE_SIZE */
 
 
 #ifdef USE_MMU
@@ -318,15 +336,13 @@ cpucache_flush:
     bne     clean_dcache
     mov     r1, #0
 #else
-    @ Index format: 31:26 = index, N:5 = segment, remainder = SBZ, assume 64-way set associative separate I/D caches
-    @ N = log2(cache size in bytes / cache line size in bytes == 32) - 6 /* index bits */ + 4 /* start offset */
     mov     r1, #0x00000000         @
 1:  @ clean_start                   @
     mcr     p15, 0, r1, c7, c10, 2  @ Clean entry by index
-    add     r0, r1, #0x00000020     @
+    add     r0, r1, #(1<<CACHEALIGN_BITS)
     mcr     p15, 0, r0, c7, c10, 2  @ Clean entry by index
 .rept INDEX_STEPS - 2 /* 2 steps already executed */
-    add     r0, r0, #0x00000020     @
+    add     r0, r0, #(1<<CACHEALIGN_BITS)
     mcr     p15, 0, r0, c7, c10, 2  @ Clean entry by index
 .endr
     adds    r1, r1, #0x04000000     @ will wrap to zero at loop end
@@ -351,15 +367,13 @@ invalidate_dcache:
     bne     invalidate_dcache
     mov     r1, #0
 #else
-    @ Index format: 31:26 = index, N:5 = segment, remainder = SBZ, assume 64-way set associative separate I/D caches
-    @ N = log2(cache size in bytes / cache line size in bytes == 32) - 6 /* index bits */ + 4 /* start offset */
     mov     r1, #0x00000000         @
 1:  @ inv_start                     @
     mcr     p15, 0, r1, c7, c14, 2  @ Clean and invalidate entry by index
-    add     r0, r1, #0x00000020     @
+    add     r0, r1, #(1<<CACHEALIGN_BITS)
     mcr     p15, 0, r0, c7, c14, 2  @ Clean and invalidate entry by index
 .rept INDEX_STEPS - 2 /* 2 steps already executed */
-    add     r0, r0, #0x00000020     @
+    add     r0, r0, #(1<<CACHEALIGN_BITS)
     mcr     p15, 0, r0, c7, c14, 2  @ Clean and invalidate entry by index
 .endr
     adds    r1, r1, #0x04000000     @ will wrap to zero at loop end
diff --git a/firmware/target/arm/s5l8700/mmu-s5l8700.S b/firmware/target/arm/s5l8700/mmu-s5l8700.S
deleted file mode 100644
index 35406b9..0000000
--- a/firmware/target/arm/s5l8700/mmu-s5l8700.S
+++ /dev/null
@@ -1,95 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * $Id$
- *
- * Copyright (C) 2006,2007 by Greg White
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-#include "config.h"
-#include "cpu.h"
-
-/** Cache coherency **/
-
-/*
- * Cleans entire DCache
- * void clean_dcache(void);
- */
-    .section   .icode, "ax", %progbits
-    .align      2
-    .global     clean_dcache
-    .type       clean_dcache, %function
-    .global     cpucache_flush      @ Alias
-clean_dcache:
-cpucache_flush:
-    @ Index format: 31:26 = index, 5:4 = segment, remainder = SBZ
-    mov     r1, #0x00000000         @
-1:  @ clean_start                   @
-    mcr     p15, 0, r1, c7, c10, 2  @ Clean entry by index
-    add     r0, r1, #0x00000010     @
-    mcr     p15, 0, r0, c7, c10, 2  @ Clean entry by index
-    add     r0, r0, #0x00000010     @
-    mcr     p15, 0, r0, c7, c10, 2  @ Clean entry by index
-    add     r0, r0, #0x00000010     @
-    mcr     p15, 0, r0, c7, c10, 2  @ Clean entry by index
-    adds    r1, r1, #0x04000000     @ will wrap to zero at loop end
-    bne     1b @ clean_start        @
-    mcr     p15, 0, r1, c7, c10, 4  @ Drain write buffer
-    bx      lr                      @ 
-    .size   clean_dcache, .-clean_dcache
-
-/*
- * Invalidate entire DCache
- * will do writeback
- * void invalidate_dcache(void);
- */
-    .section   .icode, "ax", %progbits
-    .align      2
-    .global     invalidate_dcache
-    .type       invalidate_dcache, %function
-invalidate_dcache:
-    @ Index format: 31:26 = index, 5:4 = segment, remainder = SBZ
-    mov     r1, #0x00000000         @
-1:  @ inv_start                     @
-    mcr     p15, 0, r1, c7, c14, 2  @ Clean and invalidate entry by index
-    add     r0, r1, #0x00000010     @
-    mcr     p15, 0, r0, c7, c14, 2  @ Clean and invalidate entry by index
-    add     r0, r0, #0x00000010     @
-    mcr     p15, 0, r0, c7, c14, 2  @ Clean and invalidate entry by index
-    add     r0, r0, #0x00000010     @
-    mcr     p15, 0, r0, c7, c14, 2  @ Clean and invalidate entry by index
-    adds    r1, r1, #0x04000000     @ will wrap to zero at loop end
-    bne     1b @ inv_start          @
-    mcr     p15, 0, r1, c7, c10, 4  @ Drain write buffer
-    bx      lr                      @
-    .size   invalidate_dcache, .-invalidate_dcache
-
-/*
- * Invalidate entire ICache and DCache
- * will do writeback
- * void invalidate_idcache(void);
- */
-    .section   .icode, "ax", %progbits
-    .align      2
-    .global     invalidate_idcache
-    .type       invalidate_idcache, %function
-    .global     cpucache_invalidate @ Alias
-invalidate_idcache:
-cpucache_invalidate: 
-    mov     r2, lr                  @ save lr to r2, call uses r0 and r1 only
-    bl      invalidate_dcache       @ Clean and invalidate entire DCache
-    mcr     p15, 0, r1, c7, c5, 0   @ Invalidate ICache (r1=0 from call)
-    mov     pc, r2                  @
-    .size   invalidate_idcache, .-invalidate_idcache
diff --git a/firmware/target/arm/s5l8700/mmu-target.h b/firmware/target/arm/s5l8700/mmu-target.h
deleted file mode 100644
index e2515c0..0000000
--- a/firmware/target/arm/s5l8700/mmu-target.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/***************************************************************************
- *             __________               __   ___.
- *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
- *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
- *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
- *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
- *                     \/            \/     \/    \/            \/
- * $Id$
- *
- * Copyright (C) 2006,2007 by Greg White
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-
-/*  This file MUST be included in your system-target.h file if you want arm
- *  cache coherence functions to be called (I.E. during codec load, etc).   
- */
-
-#ifndef MMU_S5L8700_H
-#define MMU_S5L8700_H
-
-/* Cleans entire DCache */
-void clean_dcache(void) ICODE_ATTR;
-
-/* Invalidate entire DCache */
-/* will do writeback */
-void invalidate_dcache(void) ICODE_ATTR;
-
-/* Invalidate entire ICache and DCache */
-/* will do writeback */
-void invalidate_idcache(void) ICODE_ATTR;
-
-#define HAVE_CPUCACHE_INVALIDATE
-#define HAVE_CPUCACHE_FLUSH
-
-#endif /* MMU_S5L8700_H */