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| author | Jens Arnold <amiconn@rockbox.org> | 2005-10-10 19:24:39 +0000 |
|---|---|---|
| committer | Jens Arnold <amiconn@rockbox.org> | 2005-10-10 19:24:39 +0000 |
| commit | f6bb10a4858f109acfdee6f83a9b333480dedb86 (patch) | |
| tree | f104dde3ef01d45e97b58ab046761320d4000acf | |
| parent | 849c2bbd9f5b489160f3de41e87af50b5a3fe414 (diff) | |
| download | rockbox-f6bb10a4858f109acfdee6f83a9b333480dedb86.zip rockbox-f6bb10a4858f109acfdee6f83a9b333480dedb86.tar.gz rockbox-f6bb10a4858f109acfdee6f83a9b333480dedb86.tar.bz2 rockbox-f6bb10a4858f109acfdee6f83a9b333480dedb86.tar.xz | |
Iriver: No write protection for flash ROM area, correct number of waitstates.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@7611 a1c6a512-1295-4272-9138-f99709370657
| -rw-r--r-- | firmware/crt0.S | 6 | ||||
| -rw-r--r-- | firmware/system.c | 4 |
2 files changed, 5 insertions, 5 deletions
diff --git a/firmware/crt0.S b/firmware/crt0.S index 4459f2e..e903bc9 100644 --- a/firmware/crt0.S +++ b/firmware/crt0.S @@ -148,9 +148,9 @@ irq_handler: /* Chip select 0 - Flash ROM */ moveq.l #0x00,%d0 /* CSAR0 - Base = 0x00000000 */ move.l %d0,(0x080,%a0) - move.l #0x001f0101,%d0 /* CSMR0 - 2M, All access, write protect */ + move.l #0x001f0001,%d0 /* CSMR0 - 2M, All access */ move.l %d0,(0x084,%a0) - move.l #0x00000d80,%d0 /* CSCR0 - 3 wait states, 16 bits, no bursts */ + move.l #0x00000180,%d0 /* CSCR0 - no wait states, 16 bits, no bursts */ move.l %d0,(0x088,%a0) /* Chip select 1 - LCD controller */ @@ -158,7 +158,7 @@ irq_handler: move.l %d0,(0x08c,%a0) moveq.l #0x75,%d0 /* CSMR1 - 64K, Only data access */ move.l %d0,(0x090,%a0) - move.l #0x00000180,%d0 /* CSCR1 - 0 wait states, 16 bits, no bursts */ + move.l #0x00000180,%d0 /* CSCR1 - no wait states, 16 bits, no bursts */ move.l %d0,(0x094,%a0) /* Chip select 2 - ATA controller */ diff --git a/firmware/system.c b/firmware/system.c index a1c4834..2eddc49 100644 --- a/firmware/system.c +++ b/firmware/system.c @@ -592,7 +592,7 @@ void set_cpu_frequency(long frequency) PLLCR &= ~1; /* Bypass mode */ timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); PLLCR = 0x11856005; - CSCR0 = 0x00000980; /* Flash: 2 wait state */ + CSCR0 = 0x00001180; /* Flash: 4 wait states */ CSCR1 = 0x00000980; /* LCD: 2 wait states */ while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. This may take up to 10ms! */ @@ -609,7 +609,7 @@ void set_cpu_frequency(long frequency) PLLCR &= ~1; /* Bypass mode */ timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); PLLCR = 0x1385e005; - CSCR0 = 0x00000180; /* Flash: 0 wait states */ + CSCR0 = 0x00000580; /* Flash: 1 wait state */ CSCR1 = 0x00000180; /* LCD: 0 wait states */ while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. This may take up to 10ms! */ |