Initial Cowon D2 commit:

* bootloader test program (basic LCD & button drivers, reads touchscreen)
* work-in-progress stubs for main build


git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16090 a1c6a512-1295-4272-9138-f99709370657

1 files changed, 110 insertions, 1 deletions

diff --git a/firmware/app.lds b/firmware/app.lds
index 9b83537..c5c4e6e 100644
--- a/firmware/app.lds
+++ b/firmware/app.lds
@@ -13,6 +13,8 @@ INPUT(target/arm/crt0-pp.o)
 INPUT(target/arm/tms320dm320/crt0.o)
 #elif CONFIG_CPU==S3C2440
 INPUT(target/arm/s3c2440/crt0.o)
+#elif defined(CPU_TCC780X)
+INPUT(target/arm/tcc780x/crt0.o)
 #elif CONFIG_CPU == PNX0101
 INPUT(target/arm/pnx0101/crt0-pnx0101.o)
 #elif CONFIG_CPU == IMX31L
@@ -75,6 +77,14 @@ INPUT(target/sh/crt0.o)
 #define DRAMORIG (0x0 + STUBOFFSET)
 #define IRAMORIG 0x1FFFC000
 #define IRAMSIZE 0x4000
+#elif defined(CPU_TCC780X)
+#define DRAMORIG 0x20000000 + STUBOFFSET
+#define ITCMORIG 0x00000000
+#define ITCMSIZE 0x1000
+#define DTCMORIG 0xA0000000
+#define DTCMSIZE 0x2000
+#define SRAMORIG 0x10000000
+#define SRAMSIZE 0xc000
 #else
 #define DRAMORIG 0x09000000 + STUBOFFSET
 #define IRAMORIG 0x0f000000
@@ -90,7 +100,12 @@ INPUT(target/sh/crt0.o)
 MEMORY
 {
     DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
-#if CONFIG_CPU != S3C2440
+#if defined(CPU_TCC780X)
+    /* Seperate data & instruction TCMs plus SRAM. */
+    ITCM : ORIGIN = ITCMORIG, LENGTH = ITCMSIZE
+    DTCM : ORIGIN = DTCMORIG, LENGTH = DTCMSIZE
+    SRAM : ORIGIN = SRAMORIG, LENGTH = SRAMSIZE
+#elif CONFIG_CPU != S3C2440
     IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
 #endif
 #if CONFIG_CPU==PNX0101
@@ -187,6 +202,100 @@ SECTIONS
        _end = .;
     } > DRAM
 
+#elif defined(CPU_TCC780X)
+    .text :
+    {
+        loadaddress = .;
+        _loadaddress = .;
+        . = ALIGN(0x200);
+        *(.init.text)
+        *(.text*)
+        *(.glue_7)
+        *(.glue_7t)
+        . = ALIGN(0x4);
+    } > DRAM
+
+    .rodata :
+    {
+        *(.rodata)  /* problems without this, dunno why */
+        *(.rodata*)
+        *(.rodata.str1.1)
+        *(.rodata.str1.4)
+        . = ALIGN(0x4);
+
+        /* Pseudo-allocate the copies of the data sections */
+        _datacopy = .;
+    } > DRAM
+
+    /* TRICK ALERT! For RAM execution, we put the .data section at the
+       same load address as the copy. Thus, we don't waste extra RAM
+       when we don't actually need the copy.  */
+    .data : AT ( _datacopy )
+    {
+        _datastart = .;
+        *(.data*)
+        . = ALIGN(0x4);
+        _dataend  = .;
+    } > DRAM
+
+    /DISCARD/ :
+    {
+        *(.eh_frame)
+    }
+
+    .vectors ITCMORIG :
+    {
+        _vectorsstart = .;
+        *(.vectors);
+        _vectorsend = .;
+    } > ITCM AT> DRAM
+
+    _vectorscopy = LOADADDR(.vectors);
+
+    .itcm :
+    {
+        _itcmstart = .;
+        *(.icode)
+        _itcmend = .;
+    } > ITCM AT> DRAM
+
+    _itcmcopy = LOADADDR(.itcm);
+    
+    .dtcm :
+    {
+        _dtcmstart = .;
+        *(.irodata)
+        *(.idata)
+        _dtcmend = .;
+    } > DTCM AT> DRAM
+
+    _dtcmcopy = LOADADDR(.dtcm);
+
+    .ibss (NOLOAD) :
+    {
+        _iedata = .;
+        *(.ibss)
+        . = ALIGN(0x4);
+        _iend = .;
+    } > SRAM
+
+    .stack :
+    {
+       *(.stack)
+       stackbegin = .;
+       . += 0x2000;
+       stackend = .;
+    } > SRAM
+
+    .bss :
+    {
+       _edata = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(0x4);
+       _end = .;
+    } > DRAM
+
 #elif CONFIG_CPU==S3C2440
     .text :
     {