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| author | Michael Sevakis <jethead71@rockbox.org> | 2010-05-08 07:45:34 +0000 |
|---|---|---|
| committer | Michael Sevakis <jethead71@rockbox.org> | 2010-05-08 07:45:34 +0000 |
| commit | a420561bf8315f60c290ea41aaa7e80f410c592d (patch) | |
| tree | 4f8f2e5e8ad8f613d3647a0239e8c40ed8b3cf8c /firmware/export | |
| parent | 7f3b3494a6a4198c59e07d54ad979b7a764250b6 (diff) | |
| download | rockbox-a420561bf8315f60c290ea41aaa7e80f410c592d.zip rockbox-a420561bf8315f60c290ea41aaa7e80f410c592d.tar.gz rockbox-a420561bf8315f60c290ea41aaa7e80f410c592d.tar.bz2 rockbox-a420561bf8315f60c290ea41aaa7e80f410c592d.tar.xz | |
Gigabeat S: Reclaim about 800K of memory that was laying unused. Get rid of DEVBSS_ATTR for this target and implement as NOCACHEBSS_ATTR. Plugin and codec buffers move so all that is now incompatible (do full update). No version increase for plugins/codecs because the loader will reject them.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25895 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/export')
| -rw-r--r-- | firmware/export/config.h | 5 | ||||
| -rw-r--r-- | firmware/export/imx31l.h | 10 |
2 files changed, 12 insertions, 3 deletions
diff --git a/firmware/export/config.h b/firmware/export/config.h index c3dd4fd..070bd95 100644 --- a/firmware/export/config.h +++ b/firmware/export/config.h @@ -826,6 +826,11 @@ Lyre prototype 1 */ #endif /* CPU_PP */ +#if CONFIG_CPU == IMX31L +#define NOCACHEBSS_ATTR __attribute__((section(".ncbss"),nocommon)) +#define NOCACHEDATA_ATTR __attribute__((section(".ncdata"),nocommon)) +#endif + #ifndef CONFIG_CORELOCK #define CONFIG_CORELOCK CORELOCK_NONE #endif diff --git a/firmware/export/imx31l.h b/firmware/export/imx31l.h index 66ae0ac..ea92d05 100644 --- a/firmware/export/imx31l.h +++ b/firmware/export/imx31l.h @@ -35,14 +35,18 @@ #define FRAME_SIZE (240*320*2) /* Rockbox framebuffer address, not retail OS */ #define FRAME_PHYS_ADDR (TTB_BASE_ADDR - FRAME_SIZE) -#define FRAME ((void *)(FRAME_PHYS_ADDR-CSD0_BASE_ADDR)) +#define FRAME ((void *)(FRAME_PHYS_ADDR+0x100000-CSD0_BASE_ADDR)) + +#define CACHEALIGN_SIZE 32 +#define NOCACHE_BASE CSD0_BASE_ADDR -#define DEVBSS_ATTR __attribute__((section(".devbss"),nocommon)) /* USBOTG */ #define USB_QHARRAY_ATTR __attribute__((section(".qharray"),nocommon,aligned(2048))) #define USB_NUM_ENDPOINTS 8 -#define USB_DEVBSS_ATTR DEVBSS_ATTR +#define USB_DEVBSS_ATTR NOCACHEBSS_ATTR #define USB_BASE OTG_BASE_ADDR +#define QHARRAY_SIZE ((64*USB_NUM_ENDPOINTS*2 + 2047) & (0xffffffff - 2047)) +#define QHARRAY_PHYS_ADDR ((FRAME_PHYS_ADDR - QHARRAY_SIZE) & (0xffffffff - 2047)) /* * AIPS 1 |