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| author | Cástor Muñoz <cmvidal@gmail.com> | 2016-07-31 03:48:11 +0200 |
|---|---|---|
| committer | Cástor Muñoz <cmvidal@gmail.com> | 2016-08-02 04:57:50 +0200 |
| commit | ef572fec523c3064cbec8df3ef7610a2a9b5df54 (patch) | |
| tree | 1b6f979c1cd8fad4f2ed6c6114763d6d7bda8156 /firmware/export | |
| parent | 3c5aa754de9c9e572232b469398a981dccfff127 (diff) | |
| download | rockbox-ef572fec523c3064cbec8df3ef7610a2a9b5df54.zip rockbox-ef572fec523c3064cbec8df3ef7610a2a9b5df54.tar.gz rockbox-ef572fec523c3064cbec8df3ef7610a2a9b5df54.tar.bz2 rockbox-ef572fec523c3064cbec8df3ef7610a2a9b5df54.tar.xz | |
iPod Nano 2G: use the new USB DesignWare driver
Change-Id: I8d1561bf4e239b55617a8d5075457a668e0c312c
Diffstat (limited to 'firmware/export')
| -rw-r--r-- | firmware/export/config/ipodnano2g.h | 7 | ||||
| -rw-r--r-- | firmware/export/s5l8700.h | 21 |
2 files changed, 24 insertions, 4 deletions
diff --git a/firmware/export/config/ipodnano2g.h b/firmware/export/config/ipodnano2g.h index 8e8f40f..aeff6ae 100644 --- a/firmware/export/config/ipodnano2g.h +++ b/firmware/export/config/ipodnano2g.h @@ -221,12 +221,15 @@ #define DEFAULT_BRIGHTNESS_SETTING 0x20 /* USB defines */ +#define CONFIG_USBOTG USBOTG_DESIGNWARE +#define USB_DW_CLOCK 0 +#define USB_DW_TURNAROUND 5 +/* logf() over USB serial (http://www.rockbox.org/wiki/PortalPlayerUsb) */ +//#define USB_ENABLE_SERIAL #define HAVE_USBSTACK #define HAVE_USB_HID_MOUSE -#define CONFIG_USBOTG USBOTG_S3C6400X #define USB_VENDOR_ID 0x05AC #define USB_PRODUCT_ID 0x1260 -#define USB_NUM_ENDPOINTS 6 #define USB_DEVBSS_ATTR __attribute__((aligned(16))) /* Define this if you can switch on/off the accessory power supply */ diff --git a/firmware/export/s5l8700.h b/firmware/export/s5l8700.h index 3444919..b559992 100644 --- a/firmware/export/s5l8700.h +++ b/firmware/export/s5l8700.h @@ -788,7 +788,24 @@ /* Synopsys OTG - S5L8701 only */ #define OTGBASE 0x38800000 #define PHYBASE 0x3C400000 -#define SYNOPSYSOTG_CLOCK 0 -#define SYNOPSYSOTG_AHBCFG (GAHBCFG_dma_enable | (GAHBCFG_INT_DMA_BURST_INCR4 << GAHBCFG_hburstlen_bitp) | GAHBCFG_glblintrmsk) + +/* OTG PHY control registers */ +#define OPHYPWR (*((uint32_t volatile*)(PHYBASE + 0x000))) +#define OPHYCLK (*((uint32_t volatile*)(PHYBASE + 0x004))) +#define ORSTCON (*((uint32_t volatile*)(PHYBASE + 0x008))) +#define OPHYUNK3 (*((uint32_t volatile*)(PHYBASE + 0x018))) +#define OPHYUNK1 (*((uint32_t volatile*)(PHYBASE + 0x01c))) +#define OPHYUNK2 (*((uint32_t volatile*)(PHYBASE + 0x044))) + +/* 7 available EPs (0b00000000011101010000000001101011), 6 used */ +#define USB_NUM_ENDPOINTS 6 + +/* Define this if the DWC implemented on this SoC does not support + dedicated FIFOs. */ +#define USB_DW_SHARED_FIFO + +/* Define this if the DWC implemented on this SoC does not support + DMA or you want to disable it. */ +// #define USB_DW_ARCH_SLAVE #endif /* CONFIG_CPU==S5L8701 */ |