Combine PortalPlayer .lds files into one for app and boot.

These nearly identical files are multiplying like rabbits as PP targets
are added and make SoC-related changes a PITA. Just include the master
.lds file from the target one as was done for bootloader USB.

Change-Id: I65e9e653030f0688b1728e32ada16abf2932e029

2 files changed, 291 insertions, 0 deletions

diff --git a/firmware/target/arm/pp/app-pp.lds b/firmware/target/arm/pp/app-pp.lds
new file mode 100644
index 0000000..e6c2b25
--- /dev/null
+++ b/firmware/target/arm/pp/app-pp.lds
@@ -0,0 +1,199 @@
+/* Will have been included from app.lds */
+ENTRY(start)
+
+OUTPUT_FORMAT(elf32-littlearm)
+OUTPUT_ARCH(arm)
+STARTUP(target/arm/pp/crt0-pp.o)
+
+#define PLUGINSIZE PLUGIN_BUFFER_SIZE
+#define CODECSIZE CODEC_SIZE
+
+#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGINSIZE - CODECSIZE
+
+#define DRAMORIG 0x00000000
+#define IRAMORIG 0x40000000
+#define IRAMSIZE 0xc000
+
+#ifdef CPU_PP502x
+#define NOCACHE_BASE 	0x10000000
+#else
+#define NOCACHE_BASE 	0x28000000
+#endif
+
+#define CACHEALIGN_SIZE 16
+
+/* End of the audio buffer, where the codec buffer starts */
+#define ENDAUDIOADDR  (DRAMORIG + DRAMSIZE)
+
+/* Where the codec buffer ends, and the plugin buffer starts */
+#define ENDADDR (ENDAUDIOADDR + CODECSIZE)
+
+MEMORY
+{
+    DRAM : ORIGIN = DRAMORIG,     LENGTH = DRAMSIZE
+    IRAM : ORIGIN = IRAMORIG,     LENGTH = IRAMSIZE
+}
+
+SECTIONS
+{
+    .text :
+    {
+        loadaddress = .;
+        _loadaddress = .;
+        . = ALIGN(0x200);
+        *(.init.text)
+        *(.text*)
+        *(.glue_7)
+        *(.glue_7t)
+        . = ALIGN(0x4);
+    } > DRAM
+
+    .rodata :
+    {
+        *(.rodata)  /* problems without this, dunno why */
+        *(.rodata*)
+        *(.rodata.str1.1)
+        *(.rodata.str1.4)
+        . = ALIGN(0x4);
+    } > DRAM
+
+    .data :
+    {
+        *(.data*)
+        . = ALIGN(0x4);
+    } > DRAM
+
+#if NOCACHE_BASE != 0
+    /* .ncdata section is placed at uncached physical alias address and is
+     * loaded at the proper cached virtual address - no copying is
+     * performed in the init code */
+    .ncdata . + NOCACHE_BASE :
+    {
+        . = ALIGN(CACHEALIGN_SIZE);
+        *(.ncdata*)
+        . = ALIGN(CACHEALIGN_SIZE);
+    } AT> DRAM
+#endif
+    
+    /DISCARD/ :
+    {
+        *(.eh_frame)
+    }
+
+    .vectors 0x0 :
+    {
+        _vectorsstart = .;
+        KEEP(*(.vectors));
+        _vectorsend = .;
+    } AT> DRAM
+
+    _vectorscopy = LOADADDR(.vectors);
+    _noloaddram  = LOADADDR(.vectors);
+
+    .ibss IRAMORIG (NOLOAD) :
+    {
+        _iedata = .;
+        *(.qharray)
+        *(.ibss*)
+        . = ALIGN(0x4);
+        _iend = .;
+    } > IRAM
+
+    .iram _iend :
+    {
+        _iramstart = .;
+        *(.icode*)
+        *(.irodata*)
+        *(.idata*)
+        . = ALIGN(0x4);
+        _iramend = .;
+    } > IRAM AT> DRAM
+
+    _iramcopy = LOADADDR(.iram);
+
+
+    .init ENDAUDIOADDR : 
+    {
+        . = ALIGN(4);
+        _initstart = .;
+        *(.init*)
+        _initend = .;
+    } AT> DRAM
+
+    _initcopy = LOADADDR(.init);
+
+    .idle_stacks (NOLOAD) :
+    {
+       *(.idle_stacks)
+#if NUM_CORES > 1
+       cpu_idlestackbegin = .;
+       . += IDLE_STACK_SIZE;
+       cpu_idlestackend = .;
+#endif
+       cop_idlestackbegin = .;
+       . += IDLE_STACK_SIZE;
+       cop_idlestackend = .;
+    } > IRAM
+
+    .stack (NOLOAD) :
+    {
+       *(.stack)
+       stackbegin = .;
+       . += 0x2000;
+       stackend = .;
+    } > IRAM
+    
+    /* .bss and .ncbss are treated as a single section to use one init loop to
+     * zero it - note "_edata" and "_end" */
+    .bss _noloaddram (NOLOAD) :
+    {
+       _edata = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(0x4);
+    } > DRAM
+
+#if NOCACHE_BASE != 0
+    .ncbss . + NOCACHE_BASE (NOLOAD):
+    {
+    	. = ALIGN(CACHEALIGN_SIZE);
+        *(.ncbss*)
+    	. = ALIGN(CACHEALIGN_SIZE);
+    } AT> DRAM
+#endif
+
+    /* This will be aligned by preceding alignments */
+    .endaddr . - NOCACHE_BASE (NOLOAD) :
+    {
+        _end = .;
+    } > DRAM
+
+    .audiobuf (NOLOAD) :
+    {
+        _audiobuffer = .;
+        . = ALIGN(0x4);
+        audiobuffer = .;
+    } > DRAM
+    
+    .audiobufend ENDAUDIOADDR (NOLOAD) :
+    {
+#ifdef IPOD_VIDEO
+        audiobufend_lds = .;
+#else
+        audiobufend = .;
+#endif
+        _audiobufend = .;
+    } > DRAM
+
+    .codec ENDAUDIOADDR (NOLOAD) :
+    {
+        codecbuf = .;
+        _codecbuf = .;
+    }
+
+    .plugin ENDADDR (NOLOAD) :
+    {
+        _pluginbuf = .;
+        pluginbuf = .;
+    }
+}
diff --git a/firmware/target/arm/pp/boot-pp.lds b/firmware/target/arm/pp/boot-pp.lds
new file mode 100644
index 0000000..602c3bf
--- /dev/null
+++ b/firmware/target/arm/pp/boot-pp.lds
@@ -0,0 +1,92 @@
+#include "config.h"
+
+ENTRY(start)
+OUTPUT_FORMAT(elf32-littlearm)
+OUTPUT_ARCH(arm)
+STARTUP(target/arm/pp/crt0-pp-bl.o)
+
+#define DRAMSIZE (MEMORYSIZE * 0x100000)
+
+#if CONFIG_CPU == PP6100
+#define DRAMORIG 0x10f00000
+#ifndef IRAMORIG
+#define IRAMORIG 0x40000000
+#endif
+#define IRAMSIZE 0x20000
+#define FLASHORIG 0x001f0000
+#define FLASHSIZE 2M
+#if CONFIG_CPU == PP5020
+#define DRAMORIG 0x10000000
+#define IRAMORIG 0x40000000
+#define IRAMSIZE 0x18000
+#define FLASHORIG 0x001f0000
+#define FLASHSIZE 2M
+#elif (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024)
+#define DRAMORIG 0x10000000
+#ifndef IRAMORIG
+#define IRAMORIG 0x40000000
+#endif
+#define IRAMSIZE 0x20000
+#define FLASHORIG 0x001f0000
+#define FLASHSIZE 2M
+#elif CONFIG_CPU == PP5002
+#define DRAMORIG 0x28000000
+#define IRAMORIG 0x40000000
+#define IRAMSIZE 0x18000
+#define FLASHORIG 0x001f0000
+#define FLASHSIZE 2M
+#endif
+
+MEMORY
+{
+    DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
+    IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
+}
+
+SECTIONS
+{
+#ifdef SANSA_PP_ERASE
+  . = IRAMORIG+0x4000;
+#else
+  . = IRAMORIG;
+#endif
+
+  .text : {
+    *(.init.text)
+    *(.text*)
+    *(.glue_7)
+    *(.glue_7t)
+  } > IRAM
+
+  .data : {
+    *(.icode)
+    *(.irodata)
+    *(.idata)
+    *(.data*)
+    *(.ncdata*)
+    *(.rodata*)
+    _dataend = . ;
+  } > IRAM
+
+  .stack (NOLOAD) : {
+     *(.stack)
+     _stackbegin = .;
+     stackbegin = .;
+     . += 0x2000;
+     _stackend = .;
+     stackend = .;
+  } > IRAM
+
+  /* The bss section is too large for IRAM - we just move it 16MB into the
+     DRAM */
+
+  . = DRAMORIG;
+  .bss . + (16*1024*1024) (NOLOAD) : {
+     _edata = .;
+     *(.bss*);
+     *(.ibss);
+     *(COMMON)
+     *(.ncbss*);
+     _end = .;
+  } > DRAM
+}