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authorJens Arnold <amiconn@rockbox.org>2008-03-26 23:45:55 +0000
committerJens Arnold <amiconn@rockbox.org>2008-03-26 23:45:55 +0000
commit06ec18d93fcead9b954c98c3d8a254281e0ea0bf (patch)
tree97aa908c9ff046e96535bc93d59ef5b136612eb7 /firmware
parent91a564e4b9c3141b7ff8595842522efe7434ec47 (diff)
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Slightly better instruction order, added comment.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16833 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware')
-rw-r--r--firmware/target/coldfire/iaudio/lcd-remote-as-iaudio.S8
-rw-r--r--firmware/target/coldfire/iaudio/m3/lcd-as-m3.S10
2 files changed, 11 insertions, 7 deletions
diff --git a/firmware/target/coldfire/iaudio/lcd-remote-as-iaudio.S b/firmware/target/coldfire/iaudio/lcd-remote-as-iaudio.S
index 18028a8..c1e38d0 100644
--- a/firmware/target/coldfire/iaudio/lcd-remote-as-iaudio.S
+++ b/firmware/target/coldfire/iaudio/lcd-remote-as-iaudio.S
@@ -32,6 +32,7 @@
/* Output 8 bits to the LCD. Instruction order is devised to maximize the
* delay between changing the data line and the CLK L->H transition, which
* makes the LCD controller sample DATA.
+ * Requires CLK = 1 on entry.
*
* Custom calling convention:
* %a0 - GPIO_OUT_ADDR
@@ -63,8 +64,8 @@
bcc.s 1f
eor.l %d6, %d0 /* 1: Flip data bit */
1:
- move.l %d0, %d1
move.l %d0, (%a0) /* Output new state and set CLK = 0*/
+ move.l %d0, %d1
eor.l %d7, %d1
bra.w .wr_bit7
@@ -72,6 +73,7 @@
/* Output 16 bits to the LCD. Instruction order is devised to maximize the
* delay between changing the data line and the CLK L->H transition, which
* makes the LCD controller sample DATA.
+ * Requires CLK = 1 on entry.
*
* Custom calling convention:
* %a0 - GPIO_OUT_ADDR
@@ -102,8 +104,8 @@
bcc.s 1f
eor.l %d6, %d0 /* 1: Flip data bit */
1:
- move.l %d0, %d1
move.l %d0, (%a0) /* Output new state and set CLK = 0*/
+ move.l %d0, %d1
eor.l %d7, %d1
nop
@@ -113,8 +115,8 @@
eor.l %d6, %d0
1:
move.l %d1, (%a0) /* Set CLK = 1 (delayed) */
- move.l %d0, %d1
move.l %d0, (%a0)
+ move.l %d0, %d1
eor.l %d7, %d1
.endm
bit_out
diff --git a/firmware/target/coldfire/iaudio/m3/lcd-as-m3.S b/firmware/target/coldfire/iaudio/m3/lcd-as-m3.S
index 5f77e01..a135ce5 100644
--- a/firmware/target/coldfire/iaudio/m3/lcd-as-m3.S
+++ b/firmware/target/coldfire/iaudio/m3/lcd-as-m3.S
@@ -32,6 +32,7 @@
/* Output 8 bits to the LCD. Instruction order is devised to maximize the
* delay between changing the data line and the CLK L->H transition, which
* makes the LCD controller sample DATA.
+ * Requires CLK = 1 on entry.
*
* Custom calling convention:
* %a0 - GPIO_OUT_ADDR
@@ -63,8 +64,8 @@
bcc.s 1f
eor.l %d6, %d0 /* 1: Flip data bit */
1:
- move.l %d0, %d1
move.l %d0, (%a0) /* Output new state and set CLK = 0*/
+ move.l %d0, %d1
eor.l %d7, %d1
bra.w .wr_bit7
@@ -72,6 +73,7 @@
/* Output 16 bits to the LCD. Instruction order is devised to maximize the
* delay between changing the data line and the CLK L->H transition, which
* makes the LCD controller sample DATA.
+ * Requires CLK = 1 on entry.
*
* Custom calling convention:
* %a0 - GPIO_OUT_ADDR
@@ -102,8 +104,8 @@
bcc.s 1f
eor.l %d6, %d0 /* 1: Flip data bit */
1:
- move.l %d0, %d1
move.l %d0, (%a0) /* Output new state and set CLK = 0*/
+ move.l %d0, %d1
eor.l %d7, %d1
nop
@@ -113,8 +115,8 @@
eor.l %d6, %d0
1:
move.l %d1, (%a0) /* Set CLK = 1 (delayed) */
- move.l %d0, %d1
move.l %d0, (%a0)
+ move.l %d0, %d1
eor.l %d7, %d1
.endm
bit_out
@@ -310,7 +312,7 @@ lcd_write_data:
movem.l (%sp), %d2-%d4/%d6-%d7/%a2-%a3
lea.l (7*4, %sp), %sp
rts
-
+
/*** The following functions are only needed for main LCDs ***/