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-rw-r--r--apps/debug_menu.c6
-rw-r--r--firmware/export/pp5020.h128
-rw-r--r--firmware/target/arm/ata-pp5020.c8
-rw-r--r--firmware/target/arm/pcm-pp.c5
4 files changed, 116 insertions, 31 deletions
diff --git a/apps/debug_menu.c b/apps/debug_menu.c
index 135c350..c939f02 100644
--- a/apps/debug_menu.c
+++ b/apps/debug_menu.c
@@ -582,6 +582,12 @@ static bool dbg_hw_info(void)
snprintf(buf, sizeof(buf), "HW rev: 0x%08x", ipod_hw_rev);
lcd_puts(0, 1, buf);
+ char pp_version[] = { (PP_VER2 >> 24) & 0xff, (PP_VER2 >> 16) & 0xff,
+ (PP_VER2 >> 8) & 0xff, (PP_VER2) & 0xff,
+ (PP_VER1 >> 24) & 0xff, (PP_VER1 >> 16) & 0xff,
+ (PP_VER1 >> 8) & 0xff, (PP_VER1) & 0xff, '\0' };
+ snprintf(buf, sizeof(buf), "PP version: %s", pp_version);
+ lcd_puts(0, 2, buf);
lcd_update();
while(1)
diff --git a/firmware/export/pp5020.h b/firmware/export/pp5020.h
index ade1f13..3d205a0 100644
--- a/firmware/export/pp5020.h
+++ b/firmware/export/pp5020.h
@@ -31,30 +31,71 @@
#define PROC_ID_COP 0xaa
/* Interrupts */
-#define CPU_INT_EN (*(volatile unsigned long*)(0x60004024))
-#define CPU_HI_INT_EN (*(volatile unsigned long*)(0x60004124))
-#define CPU_INT_CLR (*(volatile unsigned long*)(0x60004028))
-#define CPU_HI_INT_CLR (*(volatile unsigned long*)(0x60004128))
-#define CPU_INT_STAT (*(volatile unsigned long*)(0x64004000))
-#define CPU_HI_INT_STAT (*(volatile unsigned long*)(0x64004100))
-
+#define CPU_INT_STAT (*(volatile unsigned long*)(0x64004000))
+#define COP_INT_STAT (*(volatile unsigned long*)(0x60004004))
+#define CPU_FIQ_STAT (*(volatile unsigned long*)(0x60004008))
+#define COP_FIQ_STAT (*(volatile unsigned long*)(0x6000400c))
+
+#define INT_STAT (*(volatile unsigned long*)(0x60004010))
+#define INT_FORCED_STAT (*(volatile unsigned long*)(0x60004014))
+#define INT_FORCED_SET (*(volatile unsigned long*)(0x60004018))
+#define INT_FORCED_CLR (*(volatile unsigned long*)(0x6000401c))
+
+#define CPU_INT_EN_STAT (*(volatile unsigned long*)(0x60004020))
+#define CPU_INT_EN (*(volatile unsigned long*)(0x60004024))
+#define CPU_INT_CLR (*(volatile unsigned long*)(0x60004028))
+#define CPU_INT_PRIORITY (*(volatile unsigned long*)(0x6000402c))
+
+#define COP_INT_EN_STAT (*(volatile unsigned long*)(0x60004030))
+#define COP_INT_EN (*(volatile unsigned long*)(0x60004034))
+#define COP_INT_CLR (*(volatile unsigned long*)(0x60004038))
+#define COP_INT_PRIORITY (*(volatile unsigned long*)(0x6000403c))
+
+#define CPU_HI_INT_STAT (*(volatile unsigned long*)(0x64004100))
+#define COP_HI_INT_STAT (*(volatile unsigned long*)(0x60004104))
+#define CPU_HI_FIQ_STAT (*(volatile unsigned long*)(0x60004108))
+#define COP_HI_FIQ_STAT (*(volatile unsigned long*)(0x6000410c))
+
+#define HI_INT_STAT (*(volatile unsigned long*)(0x60004110))
+#define HI_INT_FORCED_STAT (*(volatile unsigned long*)(0x60004114))
+#define HI_INT_FORCED_SET (*(volatile unsigned long*)(0x60004118))
+#define HI_INT_FORCED_CLR (*(volatile unsigned long*)(0x6000411c))
+
+#define CPU_HI_INT_EN_STAT (*(volatile unsigned long*)(0x60004120))
+#define CPU_HI_INT_EN (*(volatile unsigned long*)(0x60004124))
+#define CPU_HI_INT_CLR (*(volatile unsigned long*)(0x60004128))
+#define CPU_HI_INT_PRIORITY (*(volatile unsigned long*)(0x6000412c))
+
+#define COP_HI_INT_EN_STAT (*(volatile unsigned long*)(0x60004130))
+#define COP_HI_INT_EN (*(volatile unsigned long*)(0x60004134))
+#define COP_HI_INT_CLR (*(volatile unsigned long*)(0x60004138))
+#define COP_HI_INT_PRIORITY (*(volatile unsigned long*)(0x6000413c))
+
#define TIMER1_IRQ 0
#define TIMER2_IRQ 1
+#define MAILBOX_IRQ 4
#define I2S_IRQ 10
#define IDE_IRQ 23
+#define USB_IRQ 24
+#define FIREWIRE_IRQ 25
+#define HI_IRQ 30
#define GPIO_IRQ (32+0)
#define SER0_IRQ (32+4)
#define SER1_IRQ (32+5)
#define I2C_IRQ (32+8)
-#define TIMER1_MASK (1 << TIMER1_IRQ)
-#define TIMER2_MASK (1 << TIMER2_IRQ)
-#define I2S_MASK (1 << I2S_IRQ)
-#define IDE_MASK (1 << IDE_IRQ)
-#define GPIO_MASK (1 << (GPIO_IRQ-32))
-#define SER0_MASK (1 << (SER0_IRQ-32))
-#define SER1_MASK (1 << (SER1_IRQ-32))
-#define I2C_MASK (1 << (I2C_IRQ-32))
+#define TIMER1_MASK (1 << TIMER1_IRQ)
+#define TIMER2_MASK (1 << TIMER2_IRQ)
+#define MAILBOX_MASK (1 << MAILBOX_IRQ)
+#define I2S_MASK (1 << I2S_IRQ)
+#define IDE_MASK (1 << IDE_IRQ)
+#define USB_MASK (1 << USB_IRQ)
+#define FIREWIRE_MASK (1 << FIREWIRE_IRQ)
+#define HI_MASK (1 << HI_IRQ)
+#define GPIO_MASK (1 << (GPIO_IRQ-32))
+#define SER0_MASK (1 << (SER0_IRQ-32))
+#define SER1_MASK (1 << (SER1_IRQ-32))
+#define I2C_MASK (1 << (I2C_IRQ-32))
/* Timers */
#define TIMER1_CFG (*(volatile unsigned long *)(0x60005000))
@@ -62,14 +103,22 @@
#define TIMER2_CFG (*(volatile unsigned long *)(0x60005008))
#define TIMER2_VAL (*(volatile unsigned long *)(0x6000500c))
#define USEC_TIMER (*(volatile unsigned long *)(0x60005010))
+#define RTC (*(volatile unsigned long *)(0x60005014))
/* Device Controller */
#define DEV_RS (*(volatile unsigned long *)(0x60006004))
#define DEV_EN (*(volatile unsigned long *)(0x6000600c))
-#define DEV_SYSTEM 0x4
-#define DEV_I2C 0x1000
-#define DEV_USB 0x400000
+#define DEV_SYSTEM 0x4
+#define DEV_SER0 0x40
+#define DEV_SER1 0x80
+#define DEV_I2S 0x800
+#define DEV_I2C 0x1000
+#define DEV_OPTO 0x10000
+#define DEV_PIEZO 0x10000
+#define DEV_USB 0x400000
+#define DEV_FIREWIRE 0x800000
+#define DEV_IDE0 0x2000000
/* Processors Control */
#define CPU_CTL (*(volatile unsigned long *)(0x60007000))
@@ -186,12 +235,11 @@
#define GPIOL_INT_CLR (*(volatile unsigned long *)(0x6000d17c))
/* Device initialization */
-#define DEV_INIT (*(volatile unsigned long *)(0x70000020))
+#define PP_VER1 (*(volatile unsigned long *)(0x70000000))
+#define PP_VER2 (*(volatile unsigned long *)(0x70000004))
+#define DEV_INIT (*(volatile unsigned long *)(0x70000020))
-#define INIT_USB 0x80000000
-
-/* I2C */
-#define I2C_BASE 0x7000c000
+#define INIT_USB 0x80000000
/* I2S */
#define IISCONFIG (*(volatile unsigned long*)(0x70002800))
@@ -199,10 +247,40 @@
#define IISFIFO_WR (*(volatile unsigned long*)(0x70002840))
#define IISFIFO_RD (*(volatile unsigned long*)(0x70002880))
+/* Serial Controller */
+#define SERIAL0 (*(volatile unsigned long*)(0x70006000))
+#define SERIAL1 (*(volatile unsigned long*)(0x70006040))
+
+/* I2C */
+#define I2C_BASE 0x7000c000
+
+/* EIDE Controller */
+#define IDE0_PRI_TIMING0 (*(volatile unsigned long*)(0xc3000000))
+#define IDE0_PRI_TIMING1 (*(volatile unsigned long*)(0xc3000004))
+#define IDE0_SEC_TIMING0 (*(volatile unsigned long*)(0xc3000008))
+#define IDE0_SEC_TIMING1 (*(volatile unsigned long*)(0xc300000c))
+
+#define IDE1_PRI_TIMING0 (*(volatile unsigned long*)(0xc3000010))
+#define IDE1_PRI_TIMING1 (*(volatile unsigned long*)(0xc3000014))
+#define IDE1_SEC_TIMING0 (*(volatile unsigned long*)(0xc3000018))
+#define IDE1_SEC_TIMING1 (*(volatile unsigned long*)(0xc300001c))
+
+#define IDE0_CFG (*(volatile unsigned long*)(0xc3000028))
+#define IDE1_CFG (*(volatile unsigned long*)(0xc300002c))
+
+#define IDE0_CNTRLR_STAT (*(volatile unsigned long*)(0xc30001e0))
+
/* USB controller */
-#define USB_BASE 0xc5000000
+#define USB_BASE 0xc5000000
+
+/* Firewire Controller */
+#define FIREWIRE_BASE 0xc6000000
/* Memory controller */
+#define CACHE_BASE (*(volatile unsigned long*)(0xf0000000))
+#define CACHE_INIT_BASE (*(volatile unsigned long*)(0xf0004000))
+#define CACHE_FLUSH_BASE (*(volatile unsigned long*)(0xf0008000))
+#define CACHE_INVALID_BASE (*(volatile unsigned long*)(0xf000c000))
#define MMAP0_LOGICAL (*(volatile unsigned long*)(0xf000f000))
#define MMAP0_PHYSICAL (*(volatile unsigned long*)(0xf000f004))
#define MMAP1_LOGICAL (*(volatile unsigned long*)(0xf000f008))
@@ -211,5 +289,7 @@
#define MMAP2_PHYSICAL (*(volatile unsigned long*)(0xf000f014))
#define MMAP3_LOGICAL (*(volatile unsigned long*)(0xf000f018))
#define MMAP3_PHYSICAL (*(volatile unsigned long*)(0xf000f01c))
+#define CACHE_CTRL1 (*(volatile unsigned long*)(0xf000f020))
+#define CACHE_CTRL2 (*(volatile unsigned long*)(0xf000f024))
#endif
diff --git a/firmware/target/arm/ata-pp5020.c b/firmware/target/arm/ata-pp5020.c
index f8ca773..022d165 100644
--- a/firmware/target/arm/ata-pp5020.c
+++ b/firmware/target/arm/ata-pp5020.c
@@ -43,9 +43,9 @@ bool ata_is_coldstart()
void ata_device_init()
{
/* From ipod-ide.c:ipod_ide_register() */
- outl(inl(0xc3000028) | (1 << 5), 0xc3000028);
- outl(inl(0xc3000028) & ~0x10000000, 0xc3000028);
+ IDE0_CFG |= (1<<5);
+ IDE0_CFG &=~(0x10000000); /* cpu < 65MHz */
- outl(0x10, 0xc3000000);
- outl(0x80002150, 0xc3000004);
+ IDE0_PRI_TIMING0 = 0x10;
+ IDE0_PRI_TIMING1 = 0x80002150;
}
diff --git a/firmware/target/arm/pcm-pp.c b/firmware/target/arm/pcm-pp.c
index 8912134..d8eecad 100644
--- a/firmware/target/arm/pcm-pp.c
+++ b/firmware/target/arm/pcm-pp.c
@@ -206,9 +206,8 @@ void pcm_play_dma_start(const void *addr, size_t size)
pcm_playing = true;
#if CONFIG_CPU == PP5020
- /* setup I2S interrupt for FIQ */
- outl(inl(0x6000402c) | I2S_MASK, 0x6000402c);
- CPU_INT_EN = I2S_MASK;
+ CPU_INT_PRIORITY |= I2S_MASK; /* FIQ priority for I2S */
+ CPU_INT_EN = I2S_MASK; /* Enable I2S interrupt */
#elif CONFIG_CPU == PP5024
#else
/* setup I2S interrupt for FIQ */
generated by cgit v1.1 at 2026-04-26 13:07:19 +0000