diff options
| -rw-r--r-- | firmware/drivers/uda1380.c | 2 | ||||
| -rw-r--r-- | firmware/system.c | 6 |
2 files changed, 3 insertions, 5 deletions
diff --git a/firmware/drivers/uda1380.c b/firmware/drivers/uda1380.c index 8c3cf61..67f8a6d 100644 --- a/firmware/drivers/uda1380.c +++ b/firmware/drivers/uda1380.c @@ -131,8 +131,6 @@ int uda1380_set_regs(void) /* Initialize UDA1380 codec with default register values (uda1380_defaults) */ int uda1380_init(void) { - PLLCR &= ~(1 << 22); /* Set AudioClk = FXTAL/2*/ - if (uda1380_set_regs() == -1) return -1; diff --git a/firmware/system.c b/firmware/system.c index 341e293..3253d3d 100644 --- a/firmware/system.c +++ b/firmware/system.c @@ -483,7 +483,7 @@ void set_cpu_frequency(long frequency) DCR = (DCR & ~0x000001ff) | 1; /* Refresh timer for bypass frequency */ PLLCR &= ~1; /* Bypass mode */ - PLLCR = 0x11c53005; + PLLCR = 0x11853005; CSCR0 = 0x00000980; /* Flash: 2 wait state */ CSCR1 = 0x00002580; /* LCD: 9 wait states */ while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. @@ -502,7 +502,7 @@ void set_cpu_frequency(long frequency) DCR = (DCR & ~0x000001ff) | 1; /* Refresh timer for bypass frequency */ PLLCR &= ~1; /* Bypass mode */ - PLLCR = 0x10c86001; + PLLCR = 0x10886001; CSCR0 = 0x00000180; /* Flash: 0 wait states */ CSCR1 = 0x00000980; /* LCD: 2 wait states */ while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. @@ -519,7 +519,7 @@ void set_cpu_frequency(long frequency) default: DCR = (DCR & ~0x000001ff) | 1; /* Refresh timer for bypass frequency */ - PLLCR = 0x00400000; /* Bypass mode */ + PLLCR = 0x00000000; /* Bypass mode */ CSCR0 = 0x00000180; /* Flash: 0 wait states */ CSCR1 = 0x00000180; /* LCD: 0 wait states */ cpu_frequency = CPU_FREQ; |