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-rw-r--r--firmware/export/pp5020.h5
-rw-r--r--firmware/target/arm/crt0-pp.S29
-rw-r--r--firmware/target/arm/i2s-pp.c31
-rw-r--r--firmware/target/arm/sandisk/sansa-e200/lcd-e200.c32
-rw-r--r--firmware/target/arm/system-pp502x.c41
-rw-r--r--firmware/target/arm/system-target.h3
6 files changed, 62 insertions, 79 deletions
diff --git a/firmware/export/pp5020.h b/firmware/export/pp5020.h
index 57e76f9..cbaa64d 100644
--- a/firmware/export/pp5020.h
+++ b/firmware/export/pp5020.h
@@ -189,7 +189,6 @@
#define CACHE_OP_FLUSH 0x0002
#define CACHE_OP_INVALIDATE 0x0004
-
/* GPIO Ports */
#define GPIOA_ENABLE (*(volatile unsigned long *)(0x6000d000))
#define GPIOB_ENABLE (*(volatile unsigned long *)(0x6000d004))
@@ -354,6 +353,10 @@
#define CACHE_STATUS_BASE (*(volatile unsigned long*)(0xf0004000))
#define CACHE_FLUSH_BASE (*(volatile unsigned long*)(0xf0008000))
#define CACHE_INVALID_BASE (*(volatile unsigned long*)(0xf000c000))
+#define MMAP_PHYS_READ_MASK 0x0100
+#define MMAP_PHYS_WRITE_MASK 0x0200
+#define MMAP_PHYS_DATA_MASK 0x0400
+#define MMAP_PHYS_CODE_MASK 0x0800
#define MMAP_FIRST (*(volatile unsigned long*)(0xf000f000))
#define MMAP_LAST (*(volatile unsigned long*)(0xf000f03c))
#define MMAP0_LOGICAL (*(volatile unsigned long*)(0xf000f000))
diff --git a/firmware/target/arm/crt0-pp.S b/firmware/target/arm/crt0-pp.S
index 2708ee3..858f795 100644
--- a/firmware/target/arm/crt0-pp.S
+++ b/firmware/target/arm/crt0-pp.S
@@ -42,6 +42,14 @@ start:
.equ SLEEP, 0x000000ca
.equ WAKE, 0x000000ce
.equ SLEEPING, 0x00004000
+ .equ MMAP_LOG, 0xf000f010 /* MMAP2 */
+ .equ MMAP_PHYS, 0xf000f014
+#if MEM > 32
+ .equ MMAP_MASK, 0x00007400
+#else
+ .equ MMAP_MASK, 0x00003a00
+#endif
+ .equ MMAP_FLAGS, 0x00003f84
#else
.equ PROC_ID, 0x60000000
.equ CPU_ICLR, 0x60004028
@@ -55,6 +63,14 @@ start:
.equ WAKE, 0x00000000
.equ SLEEPING, 0x80000000
.equ CACHE_CTRL, 0x6000c000
+ .equ MMAP_LOG, 0xf000f000 /* MMAP0 */
+ .equ MMAP_PHYS, 0xf000f004
+#if MEM > 32
+ .equ MMAP_MASK, 0x00003c00
+#else
+ .equ MMAP_MASK, 0x00003e00
+#endif
+ .equ MMAP_FLAGS, 0x00000f84
#endif
msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */
@@ -126,16 +142,11 @@ pad_skip:
cmp r3, r4
blo 1b
- ldr r4, =0x3f84 /* r3 and r1 values here are magic, don't touch */
+ ldr r4, =MMAP_FLAGS
orr r4, r4, r6 /* adjust for execute address */
- ldr r3, =0xf000f014
-#if MEM > 32
- mov r2, #0x7400 /* r1 appears to indicate how much memory (not in
- bytes) is remapped */
-#else
- mov r2, #0x3a00
-#endif
- ldr r1, =0xf000f010
+ ldr r3, =MMAP_PHYS
+ ldr r2, =MMAP_MASK /* ldr is more flexible */
+ ldr r1, =MMAP_LOG
mov pc, #0x40000000
remap_start:
diff --git a/firmware/target/arm/i2s-pp.c b/firmware/target/arm/i2s-pp.c
index b9e32b8..e06ee83 100644
--- a/firmware/target/arm/i2s-pp.c
+++ b/firmware/target/arm/i2s-pp.c
@@ -142,33 +142,4 @@ void i2s_reset(void)
IISFIFO_CFG |= 0x1100;
}
-#ifdef SANSA_E200
-void i2s_scale_attn_level(long frequency)
-{
- unsigned int iisfifo_cfg = IISFIFO_CFG & ~0xff;
-
- /* TODO: set this more appropriately for frequency */
- if (frequency <= CPUFREQ_DEFAULT)
- {
- /* when 4 slots full */
- /* when 4 slots empty */
- iisfifo_cfg |= 0x11;
- }
- else if (frequency < CPUFREQ_MAX)
- {
- /* when 8 slots full */
- /* when 8 slots empty */
- iisfifo_cfg |= 0x22;
- }
- else
- {
- /* when 12 slots full */
- /* when 12 slots empty */
- iisfifo_cfg |= 0x33;
- }
-
- IISFIFO_CFG = iisfifo_cfg;
-}
-#endif /* SANSA_E200 */
-
-#endif
+#endif /* CONFIG_CPU == */
diff --git a/firmware/target/arm/sandisk/sansa-e200/lcd-e200.c b/firmware/target/arm/sandisk/sansa-e200/lcd-e200.c
index 0d3a1a3..58287fc 100644
--- a/firmware/target/arm/sandisk/sansa-e200/lcd-e200.c
+++ b/firmware/target/arm/sandisk/sansa-e200/lcd-e200.c
@@ -108,9 +108,10 @@ static unsigned short r_drv_output_control = R_DRV_OUTPUT_CONTROL_NORMAL;
/* We don't know how to receive a DMA finished signal from the LCD controller
* To avoid problems with flickering, we double-buffer the framebuffer and turn
- * off DMA while updates are taking place */
+ * off DMA while updates are taking place
+ * Same alignment as in lcd-16bit.c and cache interference free */
static fb_data lcd_driver_framebuffer[LCD_FBHEIGHT][LCD_FBWIDTH]
- __attribute__((aligned(16))); /* Same alignment as in lcd-16bit.c */
+ __attribute__((aligned(16)));
#ifdef BOOTLOADER
static void lcd_init_gpio(void)
@@ -175,13 +176,15 @@ static void lcd_write_reg(unsigned int reg, unsigned int data)
/* The LCD controller gets passed the address of the framebuffer, but can only
use the physical, not the remapped, address. This is a quick and dirty way
of correcting it */
-static unsigned long phys_fb_address(unsigned long address)
+static inline unsigned long phys_fb_address(typeof (lcd_driver_framebuffer) fb)
{
- if(address < 0x10000000)
+ if ((unsigned long)fb < 0x10000000)
{
- return address + 0x10000000;
- } else {
- return address;
+ return (unsigned long)fb + 0x10000000;
+ }
+ else
+ {
+ return (unsigned long)fb;
}
}
@@ -410,7 +413,7 @@ void lcd_init_device(void)
LCD_REG_6 |= (1 << 4);
LCD_REG_5 &= ~(1 << 7);
- LCD_FB_BASE_REG = phys_fb_address((unsigned long)lcd_driver_framebuffer);
+ LCD_FB_BASE_REG = phys_fb_address(lcd_driver_framebuffer);
udelay(100000);
@@ -425,7 +428,7 @@ void lcd_init_device(void)
#else
/* Power and display already ON - switch framebuffer address and reset
settings */
- LCD_FB_BASE_REG = phys_fb_address((unsigned long)lcd_driver_framebuffer);
+ LCD_FB_BASE_REG = phys_fb_address(lcd_driver_framebuffer);
power_on = true;
display_on = true;
@@ -512,7 +515,7 @@ void lcd_update_rect(int x, int y, int width, int height)
/* TODO: It may be faster to swap the addresses of lcd_driver_framebuffer
* and lcd_framebuffer */
- dst = &lcd_driver_framebuffer[y][x];
+ dst = UNCACHED_ADDR(&lcd_driver_framebuffer[y][x]);
src = &lcd_framebuffer[y][x];
/* Copy part of the Rockbox framebuffer to the second framebuffer */
@@ -526,8 +529,6 @@ void lcd_update_rect(int x, int y, int width, int height)
/* Full width - copy as one line */
lcd_copy_buffer_rect(dst, src, LCD_WIDTH*height, 1);
}
-
- flush_icache();
}
void lcd_update(void)
@@ -538,10 +539,8 @@ void lcd_update(void)
/* TODO: It may be faster to swap the addresses of lcd_driver_framebuffer
* and lcd_framebuffer */
/* Copy the Rockbox framebuffer to the second framebuffer */
- lcd_copy_buffer_rect(&lcd_driver_framebuffer[0][0],
+ lcd_copy_buffer_rect(UNCACHED_ADDR(&lcd_driver_framebuffer[0][0]),
&lcd_framebuffer[0][0], LCD_WIDTH*LCD_HEIGHT, 1);
-
- flush_icache();
}
@@ -660,8 +659,7 @@ void lcd_yuv_blit(unsigned char * const src[3],
height >>= 1;
y = LCD_WIDTH - 1 - y;
- fb_data *dst = (fb_data*)lcd_driver_framebuffer +
- x * LCD_WIDTH + y;
+ fb_data *dst = UNCACHED_ADDR(&lcd_driver_framebuffer[x][y]);
z = stride*src_y;
yuv_src[0] = src[0] + z + src_x;
diff --git a/firmware/target/arm/system-pp502x.c b/firmware/target/arm/system-pp502x.c
index 501916c..7f6332c 100644
--- a/firmware/target/arm/system-pp502x.c
+++ b/firmware/target/arm/system-pp502x.c
@@ -98,35 +98,34 @@ void invalidate_icache(void)
{
if (CACHE_CTL & CACHE_CTL_ENABLE)
{
- unsigned i;
CACHE_OPERATION |= CACHE_OP_FLUSH | CACHE_OP_INVALIDATE;
while ((CACHE_CTL & CACHE_CTL_BUSY) != 0);
- for (i = 0x10000000; i < 0x10002000; i += 16)
- inb(i);
+ nop; nop; nop; nop;
}
}
static void init_cache(void)
{
/* Initialising the cache in the iPod bootloader prevents Rockbox from starting */
- unsigned i;
- /* cache init mode? */
+ /* cache init mode */
CACHE_CTL |= CACHE_CTL_INIT;
/* what's this do? */
CACHE_PRIORITY |= CURRENT_CORE == CPU ? 0x10 : 0x20;
- CACHE_MASK = 0xc00;
+ /* Cache if (addr & mask) >> 16 == (mask & match) >> 16:
+ * yes: 0x00000000 - 0x03ffffff
+ * no: 0x04000000 - 0x1fffffff
+ * yes: 0x20000000 - 0x23ffffff
+ * no: 0x24000000 - 0x3fffffff
+ */
+ CACHE_MASK = 0x00001c00;
CACHE_OPERATION = 0xfc0;
/* enable cache */
CACHE_CTL |= CACHE_CTL_INIT | CACHE_CTL_ENABLE | CACHE_CTL_RUN;
-
- /* fill cache from physical address - do we have a better candidate for
- an 8KB unchanging memory range? */
- for (i = 0x10000000; i < 0x10002000; i += 16)
- inb(i);
+ nop; nop; nop; nop;
}
#ifdef HAVE_ADJUSTABLE_CPU_FREQ
@@ -142,10 +141,6 @@ static void pp_set_cpu_frequency(long frequency)
while (test_and_set(&boostctrl_mtx.locked, 1)) ;
#endif
-#ifdef SANSA_E200
- i2s_scale_attn_level(CPUFREQ_DEFAULT);
-#endif
-
cpu_frequency = frequency;
clcd_clock_src = CLCD_CLOCK_SRC; /* save selected color LCD clock source */
@@ -205,10 +200,6 @@ static void pp_set_cpu_frequency(long frequency)
CLCD_CLOCK_SRC; /* dummy read (to sync the write pipeline??) */
CLCD_CLOCK_SRC = clcd_clock_src; /* restore saved value */
-#ifdef SANSA_E200
- i2s_scale_attn_level(frequency);
-#endif
-
#if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1)
boostctrl_mtx.locked = 0;
#endif
@@ -234,9 +225,15 @@ void system_init(void)
DEV_RS = 0;
outl(0x00000000, 0x60006008);
#endif
- /* Remap the flash ROM from 0x00000000 to 0x20000000. */
- MMAP3_LOGICAL = 0x20000000 | 0x3a00;
- MMAP3_PHYSICAL = 0x00000000 | 0x3f84;
+
+#if !defined(SANSA_E200) && !defined(SANSA_C200)
+ /* Remap the flash ROM on CPU, keep hidden from COP:
+ * 0x00000000-0x3fffffff = 0x20000000-0x23ffffff */
+ MMAP1_LOGICAL = 0x20003c00;
+ MMAP1_PHYSICAL = 0x00003084 |
+ MMAP_PHYS_READ_MASK | MMAP_PHYS_WRITE_MASK |
+ MMAP_PHYS_DATA_MASK | MMAP_PHYS_CODE_MASK;
+#endif
/* disable all irqs */
COP_HI_INT_CLR = -1;
diff --git a/firmware/target/arm/system-target.h b/firmware/target/arm/system-target.h
index ed8d90c..9a51350 100644
--- a/firmware/target/arm/system-target.h
+++ b/firmware/target/arm/system-target.h
@@ -70,6 +70,9 @@ static inline unsigned int current_core(void)
return core;
}
+#define UNCACHED_ADDR(a) \
+ ((typeof (a))((uintptr_t)(a) + 0x10000000))
+
#ifdef CPU_PP502x
#ifndef BOOTLOADER
generated by cgit v1.1 at 2026-05-15 23:33:56 +0000