4 files changed, 44 insertions, 6 deletions
diff --git a/firmware/target/coldfire/iaudio/x5/system-x5.c b/firmware/target/coldfire/iaudio/x5/system-x5.c
index 6be6d25..30a4f6e 100644
--- a/firmware/target/coldfire/iaudio/x5/system-x5.c
+++ b/firmware/target/coldfire/iaudio/x5/system-x5.c
@@ -42,7 +42,7 @@ void set_cpu_frequency(long frequency)
         PLLCR &= ~1;  /* Bypass mode */
         timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
         RECALC_DELAYS(CPUFREQ_MAX);
-        PLLCR = 0x13442045;
+        PLLCR = 0x03042045 | (PLLCR & 0x70C00000);
         CSCR0 = 0x00001180; /* Flash: 4 wait states */
         CSCR1 = 0x00000980; /* LCD: 2 wait states */
         while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
@@ -60,7 +60,7 @@ void set_cpu_frequency(long frequency)
         PLLCR &= ~1;  /* Bypass mode */
         timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
         RECALC_DELAYS(CPUFREQ_NORMAL);
-        PLLCR = 0x16430045;
+        PLLCR = 0x06030045 | (PLLCR & 0x70C00000);
         CSCR0 = 0x00000580; /* Flash: 1 wait state */
         CSCR1 = 0x00000180; /* LCD: 0 wait states */
         while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
@@ -77,7 +77,8 @@ void set_cpu_frequency(long frequency)
         PLLCR &= ~1;  /* Bypass mode */
         timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, true);
         RECALC_DELAYS(CPUFREQ_DEFAULT);
-        PLLCR = 0x10400200; /* Power down PLL, but keep CLSEL and CRSEL */
+        /* Power down PLL, but keep CLSEL and CRSEL */
+        PLLCR = 0x00000200 | (PLLCR & 0x70C00000);
         CSCR0 = 0x00000180; /* Flash: 0 wait states */
         CSCR1 = 0x00000180; /* LCD: 0 wait states */
         DCR = (0x8000 | DEFAULT_REFRESH_TIMER);       /* Refresh timer */
diff --git a/firmware/target/coldfire/iriver/system-iriver.c b/firmware/target/coldfire/iriver/system-iriver.c
index 3517788..43ba4ee 100644
--- a/firmware/target/coldfire/iriver/system-iriver.c
+++ b/firmware/target/coldfire/iriver/system-iriver.c
@@ -81,7 +81,7 @@ void set_cpu_frequency(long frequency)
         PLLCR &= ~1;  /* Bypass mode */
         timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
         RECALC_DELAYS(CPUFREQ_MAX);
-        PLLCR = 0x11c56005;
+        PLLCR = 0x01056005 | (PLLCR & 0x70c00000);
         CSCR0 = 0x00001180; /* Flash: 4 wait states */
         CSCR1 = 0x00001580; /* LCD: 5 wait states */
 #if CONFIG_USBOTG == USBOTG_ISP1362
@@ -108,7 +108,7 @@ void set_cpu_frequency(long frequency)
         PLLCR &= ~1;  /* Bypass mode */
         timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
         RECALC_DELAYS(CPUFREQ_NORMAL);
-        PLLCR = 0x13c5e005;
+        PLLCR = 0x0305e005 | (PLLCR & 0x70c00000);
         CSCR0 = 0x00000580; /* Flash: 1 wait state */
         CSCR1 = 0x00000180; /* LCD: 0 wait states */
 #if CONFIG_USBOTG == USBOTG_ISP1362
@@ -134,7 +134,8 @@ void set_cpu_frequency(long frequency)
         PLLCR &= ~1;  /* Bypass mode */
         timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, true);
         RECALC_DELAYS(CPUFREQ_DEFAULT);
-        PLLCR = 0x10c00200; /* Power down PLL, but keep CLSEL and CRSEL */
+        /* Power down PLL, but keep CLSEL and CRSEL */
+        PLLCR = 0x00000200 | (PLLCR & 0x70c00000);
         CSCR0 = 0x00000180; /* Flash: 0 wait states */
         CSCR1 = 0x00000180; /* LCD: 0 wait states */
 #if CONFIG_USBOTG == USBOTG_ISP1362
diff --git a/firmware/target/coldfire/system-coldfire.c b/firmware/target/coldfire/system-coldfire.c
index 66e4feb..2fc8149 100644
--- a/firmware/target/coldfire/system-coldfire.c
+++ b/firmware/target/coldfire/system-coldfire.c
@@ -310,3 +310,10 @@ int system_memory_guard(int newmode)
 
     return oldmode;
 }
+
+/* allow setting of audio clock related bits */
+void coldfire_set_pllcr_audio_bits(long bits)
+{
+    PLLCR = (PLLCR & ~0x70c00000) | (bits & 0x70c00000);
+}
+
diff --git a/firmware/target/coldfire/system-target.h b/firmware/target/coldfire/system-target.h
index 0385211..24e3fb87 100644
--- a/firmware/target/coldfire/system-target.h
+++ b/firmware/target/coldfire/system-target.h
@@ -110,6 +110,28 @@ static inline unsigned long swap32(unsigned long value)
     return value;
 }
 
+static inline unsigned long swap_odd_even32(unsigned long value)
+{
+    /*
+      result[31..24],[15.. 8] = value[23..16],[ 7.. 0]
+      result[23..16],[ 7.. 0] = value[31..24],[15.. 8]
+    */
+    unsigned long mask = 0x00FF00FF;
+
+    asm (                             /* val  = ABCD */
+        "and.l   %[val],%[mask]  \n"  /* mask = .B.D */
+        "eor.l   %[mask],%[val]  \n"  /* val  = A.C. */
+        "lsl.l   #8,%[mask]      \n"  /* mask = B.D. */
+        "lsr.l   #8,%[val]       \n"  /* val  = .A.C */
+        "or.l    %[mask],%[val]  \n"  /* val  = BADC */
+        : /* outputs */
+        [val] "+d"(value),
+        [mask]"+d"(mask)
+    );
+
+    return value;
+}
+
 static inline void invalidate_icache(void)
 {
    asm volatile ("move.l #0x01000000,%d0\n"
@@ -118,6 +140,13 @@ static inline void invalidate_icache(void)
                  "movec.l %d0,%cacr");
 }
 
+#ifdef IAUDIO_X5
+#define DEFAULT_PLLCR_AUDIO_BITS 0x10400000
+#else
+#define DEFAULT_PLLCR_AUDIO_BITS 0x10c00000
+#endif
+void coldfire_set_pllcr_audio_bits(long bits);
+
 /* 11.2896 MHz */
 #define CPUFREQ_DEFAULT_MULT 1
 #define CPUFREQ_DEFAULT      (CPUFREQ_DEFAULT_MULT * CPU_FREQ)