summaryrefslogtreecommitdiff
path: root/firmware/export/mcf5249.h (follow)
Commit message (Collapse)AuthorAge
* Put TIMER_FREQ definition in CPU-specific config, and remove timer-target.hRafaël Carré2009-06-29
| | | | | | Note : SH has TIMER_FREQ defined to CPU_FREQ, so any code wanting it must include #config.h before #cpu.h git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21560 a1c6a512-1295-4272-9138-f99709370657
* Updated our source code header to explicitly mention that we are GPL v2 orDaniel Stenberg2008-06-28
| | | | | | | | | later. We still need to hunt down snippets used that are not. 1324 modified files... http://www.rockbox.org/mail/archive/rockbox-dev-archive-2008-06/0060.shtml git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17847 a1c6a512-1295-4272-9138-f99709370657
* H300: (1) Use DMA for LCD updates, with auto-aligned line reads. Speeds up ↵Jens Arnold2006-11-02
| | | | | | LCD updates by ~ 75% at 11MHz and 45MHz. Only ~ 11% speedup at 124MHz due to (2). (2) Less aggressive LCD transfer timing at 124MHz. With the previous timing, slightly corrupted display contents was reported, and with DMA transfers at least 4 waitstates are needed to make updates work at all. * A table in system-iriver.c shows settings for all integer multiples of the base clock frequency (info for developers, not yet complete). git-svn-id: svn://svn.rockbox.org/rockbox/trunk@11418 a1c6a512-1295-4272-9138-f99709370657
* Fixup of the MCF5249 memory mapped register definitions.Jens Arnold2005-11-05
| | | | git-svn-id: svn://svn.rockbox.org/rockbox/trunk@7755 a1c6a512-1295-4272-9138-f99709370657
* Corrected UART register namesLinus Nielsen Feltzing2005-08-13
| | | | git-svn-id: svn://svn.rockbox.org/rockbox/trunk@7325 a1c6a512-1295-4272-9138-f99709370657
* Iriver: First attempt at recording. Use Info->Debug->PCM recording to test ↵Andy2005-06-19
| | | | | | recording of wav-files. Seams to work fine except occasional 100 ms noise at pos 100 ms (not later) so initialization or synch problem.. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@6763 a1c6a512-1295-4272-9138-f99709370657
* ColdFire: DCR is a 16-bit registerLinus Nielsen Feltzing2005-06-08
| | | | git-svn-id: svn://svn.rockbox.org/rockbox/trunk@6604 a1c6a512-1295-4272-9138-f99709370657
* Added DMA register definitionsLinus Nielsen Feltzing2005-03-18
| | | | git-svn-id: svn://svn.rockbox.org/rockbox/trunk@6202 a1c6a512-1295-4272-9138-f99709370657
* Correct size for the DCRx registersLinus Nielsen Feltzing2005-02-16
| | | | git-svn-id: svn://svn.rockbox.org/rockbox/trunk@5993 a1c6a512-1295-4272-9138-f99709370657
* Correct size for the BCRx registersLinus Nielsen Feltzing2005-02-16
| | | | git-svn-id: svn://svn.rockbox.org/rockbox/trunk@5992 a1c6a512-1295-4272-9138-f99709370657
* Made the Coldfire registers volatile, rename PLLCONTROL to PLLCRLinus Nielsen Feltzing2005-02-14
| | | | git-svn-id: svn://svn.rockbox.org/rockbox/trunk@5941 a1c6a512-1295-4272-9138-f99709370657
* The timer registers are 16-bitLinus Nielsen Feltzing2004-10-27
| | | | git-svn-id: svn://svn.rockbox.org/rockbox/trunk@5364 a1c6a512-1295-4272-9138-f99709370657
* CPU definitions for MCF5249Linus Nielsen Feltzing2004-10-06
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@5183 a1c6a512-1295-4272-9138-f99709370657
generated by cgit v1.1 at 2026-04-25 11:13:24 +0000