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path: root/firmware/target/arm/system-target.h (follow)
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* Move PP-specific headers to pp/ directoryRafaël Carré2012-01-03
| | | | git-svn-id: svn://svn.rockbox.org/rockbox/trunk@31530 a1c6a512-1295-4272-9138-f99709370657
* firewire/usb_remove/insert_int: move to system-target.hRafaël Carré2011-12-31
| | | | git-svn-id: svn://svn.rockbox.org/rockbox/trunk@31491 a1c6a512-1295-4272-9138-f99709370657
* usb_plugged() is PP onlyRafaël Carré2011-12-31
| | | | git-svn-id: svn://svn.rockbox.org/rockbox/trunk@31489 a1c6a512-1295-4272-9138-f99709370657
* move usb_pin_init() declaration to PP's system-target.hRafaël Carré2011-12-31
| | | | | | | remove duplicate usb_detect() declaration Remove all content from empty usb-target.h files git-svn-id: svn://svn.rockbox.org/rockbox/trunk@31488 a1c6a512-1295-4272-9138-f99709370657
* Commit to certain names for cache coherency APIs and discard the aliases.Michael Sevakis2011-12-17
| | | | | | | Wouldn't surprise me a bit to get some non-green. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@31339 a1c6a512-1295-4272-9138-f99709370657
* Set the default battery capacity for ipod video properly depending on ↵Frank Gevaerts2011-07-19
| | | | | | | | | detected RAM size. Also set up a callback for the battery capacity setting (for all players) so changes take effect without having to reboot. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@30170 a1c6a512-1295-4272-9138-f99709370657
* Bootloader USB mode for PP502x. Enable only on GoGear SA9200 for the time ↵Michael Sevakis2011-01-15
| | | | | | being. Add HAVE_BOOTLOADER_USB_MODE to config if BOOTLOADER is defined to enable it. Clean up some kernel stuff a little to support it. Mess up a bunch of other stuff (hopefully not too badly). git-svn-id: svn://svn.rockbox.org/rockbox/trunk@29053 a1c6a512-1295-4272-9138-f99709370657
* Change alignment macros to allow further performance optimization. Define ↵Andree Buschmann2010-11-21
| | | | | | the CACHEALIGN macros for all ARM CPUs, the used alignment size is derived from CACHEALIGN_BITS which has been defined for each supported ARM CPU with r28619. The default alignment size for ARM is set to 32 bytes as new -- not yet supported -- ARM CPUs will most probably need this alignment. To be able to differ between ARM and other CPUs a new macro called MEM_ALIGN_ATTR is introduced. This equals CACHEALIGN_ATTR for ARM, 16 byte alignment for Coldfire and is kept empty for other CPUs. MEM_ALIGN_ATTR is available system wide. From measurements it is expected that the usage of MEM_ALIGN_ATTR can give significant performance gain on ARM11 CPUs. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28625 a1c6a512-1295-4272-9138-f99709370657
* Rename cache coherency functions.Thomas Martitz2010-09-08
| | | | | | | | | | | | | | The old cache coherency function names where wrong and misleading. The new names are (purposely different from vendor manuals) * commit_* (write-back only) * discard_* (removing lines from cache only) * commit_discard_* (write-back and removing lines from cache) It's suspected the old names have led to wrong uses. The old names still exist (as aliases) so every call via the old names need to be double checked and changed to the new name. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28045 a1c6a512-1295-4272-9138-f99709370657
* ipodvideo: detect ram size at boot (doesn't actually get USED yet)Torne Wuff2010-08-29
| | | | | | | | | This is the first step to allowing a single build which will work on any ipodvideo. A global variable, probed_ramsize, is initialised to either 32 or 64 early in boot. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@27937 a1c6a512-1295-4272-9138-f99709370657
* Move CACHEALIGN_BITS to cpu headersRafaël Carré2010-04-13
| | | | git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25633 a1c6a512-1295-4272-9138-f99709370657
* Use STORAGE_WANTS_ALIGN to make clear it's not a strict necessityRafaël Carré2010-03-26
| | | | | | Define PROC_NEEDS_CACHEALIGN only for PP git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25339 a1c6a512-1295-4272-9138-f99709370657
* Make storage alignement use cache alignement macrosRafaël Carré2010-03-25
| | | | | | | | | | Introduce STORAGE_ALIGN_DOWN, STORAGE_PAD (using new CACHE_PAD) and STORAGE_OVERLAP (using new CACHE_OVERLAP), make them useful only when PROC_NEEDS_CACHEALIGN and STORAGE_NEEDS_ALIGN are defined Modify PP and nano2g system-target.h accordingly git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25336 a1c6a512-1295-4272-9138-f99709370657
* Remove some unused declarationsBertrik Sikken2009-05-21
| | | | git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21010 a1c6a512-1295-4272-9138-f99709370657
* Make basic cache functions into calls, and get rid of ↵Michael Sevakis2009-02-11
| | | | | | CACHE_FUNCTION_WRAPPERS and CACHE_FUNCTIONS_AS_CALL macros. Rename flush/invalidate_icache to cpucache_flush/invalidate. They're inlined only if an implementation isn't provided by defining HAVE_CPUCACHE_FLUSH/INVALIDATE. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19971 a1c6a512-1295-4272-9138-f99709370657
* Updated our source code header to explicitly mention that we are GPL v2 orDaniel Stenberg2008-06-28
| | | | | | | | | later. We still need to hunt down snippets used that are not. 1324 modified files... http://www.rockbox.org/mail/archive/rockbox-dev-archive-2008-06/0060.shtml git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17847 a1c6a512-1295-4272-9138-f99709370657
* Fix freezing of some builds on PP5002. The PP5002 needs the not-sleep-at ↵Jens Arnold2008-04-20
| | | | | | 0xNNNNNNN0-addresses fix everywhere when caching is enabled, not only in core_sleep(). Introduced a pair of inline functions to sleep and wake cores on PP for consistency. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17192 a1c6a512-1295-4272-9138-f99709370657
* Enable nocache sections using the linker. PP5022/4 must use SW_CORELOCK now ↵Michael Sevakis2008-04-06
| | | | | | with shared variables in DRAM (it seems swp(b) is at least partially broken on all PP or I'm doing something very wrong here :\). For core-shared data use SHAREDBSS/DATA_ATTR. NOCACHEBSS/DATA_ATTR is available whether or not single core is forced for static peripheral-DMA buffer allocation without use of the UNCACHED_ADDR macro in code and is likely useful on a non-PP target with a data cache (although not actually enabled in config.h and the .lds's in this commit). git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16981 a1c6a512-1295-4272-9138-f99709370657
* Enable dualcore for the pp5002 processor by adding the needed cache handling ↵Michael Sevakis2007-11-27
| | | | | | and sleep/wakeup sync to the kernel. Refine some handling of fw/bl startup for all. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@15827 a1c6a512-1295-4272-9138-f99709370657
* Add some CACHEALIGN_* macros and a helper function to assist in aligning ↵Michael Sevakis2007-11-08
| | | | | | data and buffers on PortalPlayer processors to cache line boundaries. They're noops when PROC_NEED_CACHEALIGN isn't defined. Go safe and increase the value to 32 since I'm not sure yet if 16 is sufficient - changing that is a one-liner. Add helper to plugin API which will be needed shortly. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@15523 a1c6a512-1295-4272-9138-f99709370657
* Finally full multicore support for PortalPlayer 502x targets with an eye ↵Michael Sevakis2007-10-16
| | | | | | towards the possibility of other types. All SVN targets the low-lag code to speed up blocking operations. Most files are modified here simple due to a name change to actually support a real event object and a param change to create_thread. Add some use of new features but just sit on things for a bit and leave full integration for later. Work will continue on to address size on sensitive targets and simplify things if possible. Any PP target having problems with SWP can easily be changed to sw corelocks with one #define change in config.h though only PP5020 has shown an issue and seems to work without any difficulties. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@15134 a1c6a512-1295-4272-9138-f99709370657
* Unify PCM interface just above the hardware driver level for all targets ↵Michael Sevakis2007-10-06
| | | | | | including the sims. Perform lockout of audio callback when changing states. Weird new playback or recording trouble? Check before and after this revision first though things seem quite sound. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@15006 a1c6a512-1295-4272-9138-f99709370657
* The UNCACHED_ADDR macro should not adjust addresses in the bootloader.Michael Sevakis2007-10-04
| | | | git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14981 a1c6a512-1295-4272-9138-f99709370657
* PP502x: Make RAM physical addresses uncached. Cache the flash ROM on targets ↵Michael Sevakis2007-10-04
| | | | | | with one. Kill all the now unneeded cache flushing and i2s tweaking on e200 so clicking is no worry. Write the driver framebuffer at uncached addresses. Recording monitoring may be a little noisy in the left channel for the moment when not boosted and will be addressed. All seems to work as advertised including flash ROM dump. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14976 a1c6a512-1295-4272-9138-f99709370657
* Compile Portal Player bootloaders as single core. Cleanup the startup code ↵Michael Sevakis2007-09-29
| | | | | | for bootloaders. Remove cop stack entirely and keep IRAM use down on all relevant targets - just use the 128-byte idle stack. Use the inline asm version of current_core for pp5002 as well. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14898 a1c6a512-1295-4272-9138-f99709370657
* Anti-red: No need for COP initialization in the bootloaders nor idle stacks.Michael Sevakis2007-09-28
| | | | git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14880 a1c6a512-1295-4272-9138-f99709370657
* Commit a subset of the dual core changes that have to do with cache ↵Michael Sevakis2007-09-28
| | | | | | handling, stacks, firmware startup and thread startup. Tested on e200, H10-20GB, iPod Color and 5.5G. Thread function return implemented for all targets. Some changes to plugins to follow shortly. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14879 a1c6a512-1295-4272-9138-f99709370657
* More interupt/timer workKarl Kurbjun2007-09-22
| | | | git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14823 a1c6a512-1295-4272-9138-f99709370657
* m:robe 500i port: Add primitives for the SPI bus and start moving toward ↵Catalin Patulea2007-09-21
| | | | | | new-style register definitions. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14798 a1c6a512-1295-4272-9138-f99709370657
* Hopefully fix all the errors/warningsJonathan Gordon2007-09-20
| | | | git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14764 a1c6a512-1295-4272-9138-f99709370657
* Beginning of an M:Robe 500i port. Currently only in the bootloader stage. ↵Karl Kurbjun2007-09-20
| | | | | | Needs another piece of code to start the boot process - will be in the wiki. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14763 a1c6a512-1295-4272-9138-f99709370657
* PP502x: Clock setup cleanup. Barry Wardell2007-07-31
| | | | | | | | * Prepare sleep mode by adding CPUFREQ_SLEEP, as was done previsouly with PP5002. This is already confirmed working on PP5020 (H10), PP5022 (mini2g) and PP5024 (Sansa), but a lot of functions in rockbox will probably hang because the microsecond timer isn't running in this mode. * Simplify set_cpu_frequency() somewhat to make it more like the PP5002 version. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14106 a1c6a512-1295-4272-9138-f99709370657
* PP5002: Clock setup cleanup. * Switch to 80MHz when boosted like on the ↵Jens Arnold2007-07-31
| | | | | | other PP targets. * Prepare sleep mode by adding CPUFREQ_SLEEP. This is already confirmed working, but a lot of functions in rockbox will probably hang because the microsecond timer isn't running in this mode. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14096 a1c6a512-1295-4272-9138-f99709370657
* Clean up PP502x CPU clock setup code and use the full 80MHz when boosted.Jens Arnold2007-07-26
| | | | git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14004 a1c6a512-1295-4272-9138-f99709370657
* Remove the hack which read the ipod hardware revision from flash in the ↵Dave Chapman2007-07-25
| | | | | | bootloader and passed it to Rockbox via a fixed address in SDRAM. Rockbox now remaps flash and so can just read the value itself. Also clean up the debug menu a little - only display the hw revision for ipods, and add the lcd_type variable to indicate the type of LCD (0 or 1) for ipod Color/Photo. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13986 a1c6a512-1295-4272-9138-f99709370657
* Improved CPU clock setup for PP502x. PP5020 and PP5022 are not register ↵Jens Arnold2007-07-02
| | | | | | compatible here, so define the PP5022 targets properly, and introduce a CPU_PP502x macro for easier family check. Improves stability on PP5020 (less freezing, tested with Mini G1) and reduces clock change penalty (500us on PP5020; uses the relock bit on PP5022). git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13763 a1c6a512-1295-4272-9138-f99709370657
* Heh. Better way to load the PROCESSOR_ID address. Thanks Thom. :)Michael Sevakis2007-04-14
| | | | git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13156 a1c6a512-1295-4272-9138-f99709370657
* PP5020/PP5024: Add ASM optimized inline current_core.Michael Sevakis2007-04-14
| | | | git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13155 a1c6a512-1295-4272-9138-f99709370657
* Do the target shuffle again a better way by including from higher levelsMichael Sevakis2007-04-14
| | | | git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13151 a1c6a512-1295-4272-9138-f99709370657
* Portal Player: Add invalidate_icache and flush_icache. Flush the cache on ↵Michael Sevakis2007-04-13
the core for newborn threads. In doing so, move more ARM stuff to the target tree and organize it to make a clean job of it. If anything isn't appropriate for some particular device give a hollar or even just fix it by some added #ifdefing. I was informed that the PP targets are register compatible so I'm going off that advice. The Sansa likes it though. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13144 a1c6a512-1295-4272-9138-f99709370657
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