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| author | Linus Nielsen Feltzing <linus@haxx.se> | 2005-06-08 07:37:32 +0000 |
|---|---|---|
| committer | Linus Nielsen Feltzing <linus@haxx.se> | 2005-06-08 07:37:32 +0000 |
| commit | cff83c78c7ddce36bd42ec992e201f947f7b4a0a (patch) | |
| tree | 3e8c83f51807f7c88b2b591ce35279deb349abda | |
| parent | aa9c329dbee3c91c7473c174a9502ec3a7b3df43 (diff) | |
| download | rockbox-cff83c78c7ddce36bd42ec992e201f947f7b4a0a.zip rockbox-cff83c78c7ddce36bd42ec992e201f947f7b4a0a.tar.gz rockbox-cff83c78c7ddce36bd42ec992e201f947f7b4a0a.tar.bz2 rockbox-cff83c78c7ddce36bd42ec992e201f947f7b4a0a.tar.xz | |
ColdFire: DCR is a 16-bit register
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@6604 a1c6a512-1295-4272-9138-f99709370657
| -rw-r--r-- | firmware/crt0.S | 4 | ||||
| -rw-r--r-- | firmware/export/mcf5249.h | 2 | ||||
| -rw-r--r-- | firmware/system.c | 10 |
3 files changed, 8 insertions, 8 deletions
diff --git a/firmware/crt0.S b/firmware/crt0.S index ee8beb7..887f7de 100644 --- a/firmware/crt0.S +++ b/firmware/crt0.S @@ -190,8 +190,8 @@ irq_handler: /* Set up the DRAM controller. The refresh is based on the 11.2896MHz clock (5.6448MHz bus frequency). We haven't yet started the PLL */ - move.l #0x80010000,%d0 - move.l %d0,(0x100,%a0) /* DCR - Synchronous, 32 cycle refresh */ + move.w #0x8001,%d0 + move.w %d0,(0x100,%a0) /* DCR - Synchronous, 32 cycle refresh */ /* Note: we place the SDRAM on an 0x1000000 (16M) offset because the 5249 BGA chip has a fault which disables the use of A24. The diff --git a/firmware/export/mcf5249.h b/firmware/export/mcf5249.h index d4ed284..398b311 100644 --- a/firmware/export/mcf5249.h +++ b/firmware/export/mcf5249.h @@ -44,7 +44,7 @@ #define CSMR3 (*(volatile unsigned long *)(MBAR + 0x0a8)) #define CSCR3 (*(volatile unsigned long *)(MBAR + 0x0ac)) -#define DCR (*(volatile unsigned long *)(MBAR + 0x100)) +#define DCR (*(volatile unsigned short *)(MBAR + 0x100)) #define DACR0 (*(volatile unsigned long *)(MBAR + 0x108)) #define DMR0 (*(volatile unsigned long *)(MBAR + 0x10c)) #define DACR1 (*(volatile unsigned long *)(MBAR + 0x110)) diff --git a/firmware/system.c b/firmware/system.c index be6be1d..d095e15 100644 --- a/firmware/system.c +++ b/firmware/system.c @@ -480,7 +480,7 @@ void set_cpu_frequency(long frequency) switch(frequency) { case CPUFREQ_MAX: - DCR = (DCR & ~0x000001ff) | 1; /* Refresh timer for bypass + DCR = (DCR & ~0x01ff) | 1; /* Refresh timer for bypass frequency */ PLLCR &= ~1; /* Bypass mode */ PLLCR = 0x11853005; @@ -488,7 +488,7 @@ void set_cpu_frequency(long frequency) CSCR1 = 0x00002580; /* LCD: 9 wait states */ while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. This may take up to 10ms! */ - DCR = (DCR & ~0x000001ff) | 28; /* Refresh timer */ + DCR = (DCR & ~0x01ff) | 28; /* Refresh timer */ cpu_frequency = CPUFREQ_MAX; tick_start(1000/HZ); IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ @@ -499,7 +499,7 @@ void set_cpu_frequency(long frequency) break; case CPUFREQ_NORMAL: - DCR = (DCR & ~0x000001ff) | 1; /* Refresh timer for bypass + DCR = (DCR & ~0x01ff) | 1; /* Refresh timer for bypass frequency */ PLLCR &= ~1; /* Bypass mode */ PLLCR = 0x10886001; @@ -507,7 +507,7 @@ void set_cpu_frequency(long frequency) CSCR1 = 0x00000980; /* LCD: 2 wait states */ while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. This may take up to 10ms! */ - DCR = (DCR & ~0x000001ff) | 10; /* Refresh timer */ + DCR = (DCR & ~0x01ff) | 10; /* Refresh timer */ cpu_frequency = CPUFREQ_NORMAL; tick_start(1000/HZ); IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ @@ -517,7 +517,7 @@ void set_cpu_frequency(long frequency) MFDR2 = 0x13; break; default: - DCR = (DCR & ~0x000001ff) | 1; /* Refresh timer for bypass + DCR = (DCR & ~0x01ff) | 1; /* Refresh timer for bypass frequency */ PLLCR = 0x00000000; /* Bypass mode */ CSCR0 = 0x00000180; /* Flash: 0 wait states */ |