| Commit message (Collapse) | Author | Age |
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Add lua code to check whether ei/di and ext instructions are supported. This
is unclear since xburst is somewhere between mips32r1 and mips32r2. Details
results are below, but in summary: they don't work (ei has no effect, di/ext
cause illegal instruction exceptions)
> ./hwstub_shell -q -b -e 'require("jz/misc"); JZ.misc.enable_sram()' \
-f lua/xburst.lua -e "XBURST.test_ext_inst(0xb32d0000)"
[...]
Selecting soc jz4760b. Redirecting HW to hwstub.soc.jz4760b
data: d7168acf
error: lua/xburst.lua:209: call failed
trapped exception in call
> ./hwstub_shell -q -b -e 'require("jz/misc"); JZ.misc.enable_sram()' \
-f lua/xburst.lua -e "XBURST.test_ei_di_inst(0xb32d0000)"
[...]
Selecting soc jz4760b. Redirecting HW to hwstub.soc.jz4760b
Testing ei
Test SR
Enable interrupts with CP0
SR: 0x1
Disable interrupts with CP0
SR: 0x0
Test ei/di
Enable interrupts with ei
SR: 0x0
Disable interrupts with di
error: lua/xburst.lua:244: call failed
trapped exception in call
Change-Id: I2e162b5dd5e70488bcd8b58f3ca401a3ecab3c4b
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Change-Id: I76f7cffc700e8051d02936c24e8a70a0f8925edf
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Change-Id: I14987d9783dd371f4990a5bcfbfb2d1c0c9be213
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The JZ misc allows to enable and test SRAM.
The XBurst code uses the coprocessor interface to analyse the cpu. It also
provides a test platform for various features like EBASE and exceptions.
I was able to test and confirm that on jz4760b (thus xburst), EBASE works
(but top 2 bits are not controllable and always 01). The processor claims
to support vector interrupts but this is untested. The values in ConfigX
are not to be trusted blindly, clearly some are wrong. I tried to use the
JZ4780 Config7 "ebase gate" to change bit 30 of EBASE but it does not work,
which suggests that JZ480 uses a newer version of XBurst. Detailled log below:
> ./hwstub_shell -q -f lua/xburst.lua -e "XBURST.init()"
[...]
XBurst:
PRId: 0x2ed0024f
CPU: JZ4760(B)
Config: 0x80000483
Architecture Type: MIPS32
Architecture Level: Release 2 (or more)
MMU Type: Standard TLB
Config1: 0x3e63318a
MMU Size: 32
ICache
Sets per way: 128
Ways: 4
Line size: 32
DCache
Sets per way: 128
Ways: 4
Line size: 32
FPU: no
Config2: 0x80000000
Config3: 0x20
Vectored interrupt: yes
Config7: 0x0
> ./hwstub_shell -q -e 'require("jz/misc"); JZ.misc.enable_sram()' \
-f lua/xburst.lua -e "XBURST.test_ebase(0x80000000);XBURST.test_ebase(0xb32d0000)
[...]
Testing EBASE...
Disable BEV
SR value: 0x2000fc00
EBASE value: 0x80000000
Value after writing 0x80000000: 0x80000000
Value after writing 0x80040000: 0x80040000
Test result: EBase seems to work
Disable config7 gate: write 0x0 to Config7
Value after writing 0xfffff000: 0xbffff000
Enable config7 gate: write 0x80 to Config7
Value after writing 0xc0000000: 0x80000000
Config7 result: Config7 gate does not work
Exception test with EBASE at 0x80000000...
Writing instructions to memory
Old SR: 0x2000fc00
New SR: 0xfc00
EBASE: 80000000
Before: cafebabe
After: deadbeef
Exception result: Exception and EBASE are working
Testing EBASE...
Disable BEV
SR value: 0x2000fc00
EBASE value: 0x80000000
Value after writing 0x80000000: 0x80000000
Value after writing 0x80040000: 0x80040000
Test result: EBase seems to work
Disable config7 gate: write 0x0 to Config7
Value after writing 0xfffff000: 0xbffff000
Enable config7 gate: write 0x80 to Config7
Value after writing 0xc0000000: 0x80000000
Config7 result: Config7 gate does not work
Exception test with EBASE at 0xb32d0000...
Writing instructions to memory
Old SR: 0x2000fc00
New SR: 0xfc00
EBASE: b32d0000
Before: cafebabe
After: deadbeef
Exception result: Exception and EBASE are working
Change-Id: I894227981a141a8c14419b36ed9f519baf145ad1
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Change-Id: Ie46ec293fcd5a16143818e77cd6c79cc08620fb5
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The jz code can do several useful things like dumping the IPL and SPL.
The Fiio code can play with backlight and has code do dump the IPL
and SPL with the correct parameters (extracted by reverse engineering).
Change-Id: I317b3174f5db8d38c9a56670c1d45565142ec208
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Also use this opportunity to cleanup support for multiple devices: the shell
now supports dynamic changes in the device and will call init() everytime
a new device is selected, to prepare a new environment. The shell now
honors register width on register read/write. The shell also provides access
to variants as follows by creating a subtable under the register using the
variant type in UPPER case and having the same layout as a register.
For example if register HW.GPIO.DIR has variants "set" and "clr", those can
be used like this:
HW.GPIO.DIR.SET.write(0xff)
HW.GPIO.DIR.CLR.write(0xff00)
Change-Id: I943947fa98bce875de0cba4338e8b7196a4c1165
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Change-Id: I5fbd1799b958bedbe74f91bdcdd8a544e15d2a78
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With this you can upload and run code on DSP core in atj213x.
The files can be produced using as2181. You can download
this assembler from https://github.com/wodz/as2181
You should use extended mode (-x switch) since DSP core
in atj is non standard and uses 24bit operands.
PX register has different meaning as well and is used as MSB
when loading other registers with immediates (immediate field
is 16bit in instruction so to set register to 24bit value
you need to store MSB in PX prior to this).
MAC MR is 56bit accordingly.
HIP interface seems to be mapped at standard addresses
(except that regular 218x doesn't have HIP).
Have a fun!
Change-Id: I9a80ca0dd3718ba8435ae8579bfffa66e067e022
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This uses slightly hacked luaprompt to provide all the goodis.
See https://github.com/dpapavas/luaprompt for original.
Change-Id: Iedddb79abae5809299322bc215722dd928c35cca
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Change-Id: Ie09d0db21831b79255da858bada7382a08ff4eef
Reviewed-on: http://gerrit.rockbox.org/1052
Reviewed-by: Marcin Bukat <marcin.bukat@gmail.com>
Tested: Marcin Bukat <marcin.bukat@gmail.com>
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Change-Id: I3ab32996b4b6603fd7d66eee5b3bfd795b79eee1
Reviewed-on: http://gerrit.rockbox.org/1049
Reviewed-by: Marcin Bukat <marcin.bukat@gmail.com>
Tested: Marcin Bukat <marcin.bukat@gmail.com>
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Change-Id: I566694f19dfb110dbf245be7b7f139a4c616e16b
Reviewed-on: http://gerrit.rockbox.org/1041
Reviewed-by: Amaury Pouly <amaury.pouly@gmail.com>
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Change-Id: Ie0c68925f933aebeb9b3497800a29de2d69fead2
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Change-Id: I8fe15ad8207ac7098944bb85d6b66b91b9858e8f
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Change-Id: If188a01adee2a0e1c7a46c424a0a9cde9f666831
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Change-Id: I008a55675054c86fd206cc5248f2bd9475e80b49
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- drop support for PP500x: it's very different from other PP and although
it would be possible to support them, I don't have one to test the code
- make sure only the CPU is started
- add PP descriptor to report chip ID and revision
- add code in shell and lua to support pp (no register description yet)
- compile for ARMv4 because PP502x is an ARM7TDMI
Change-Id: I36c4e465dfc2cfdfe7433b2f65cc8f6f0720fe62
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Change-Id: I7e85101eca7dfc0f68c215936be4aa19749923ad
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Change-Id: Ia9576162b3b28d3778fe479cc321c879d73247c6
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Change-Id: I30a2cedb1170abbee5a80c33206c147eb4207ca5
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Change-Id: I535d54bc3fb2263c174b7ae983ea4f5ed68e6390
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Change-Id: I38cf0b5808443d5c19ebddb329c2a1636bcc4b28
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Change-Id: Iff1b4f40affb88c104e7322e25cdbe34f8886476
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Change-Id: I61fc58e3c97a3666eac98d21226865181b85eef1
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Change-Id: I85ac57117911544b65ccd56eb16303e30be67cab
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Change-Id: I9266ec6db457b1d649cbdcb6c9bd1d0f3223b867
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Change-Id: I1e5f87f15f0ca9586d8185316ffcaeef6d9d4d38
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Change-Id: I8d581ec906ec2bab0d983aacfb0e8479b77d0c57
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Change-Id: I9fe5da773705ec4c3d014b8ac7f78ad614e20a30
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Change-Id: I6787e682a9e22cb34e6d94d25bf68d7575d784c4
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Change-Id: I94f764c0fcfb47bd9ccafe23f6d6079b42f23826
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Change-Id: I4dee8e115e282d1d6540013c9b9f1263e30690de
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Change-Id: I5316cc9fd9addfca8a674628695fed1c1bf9269f
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Change-Id: I432853fb4171f07ed23b73dc0499814fe8ce8748
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Change-Id: Ice5f509a2e0d2114436d4760f338b9203ef96691
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